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gem5.git
2018-02-07 Nikos Nikolerisarch-arm: Turn dc ivac to dc civac when some conditions... commit | commitdiff | tree
2018-02-07 Nikos Nikolerisarch-arm: Fix printing of the data cache maintenance... commit | commitdiff | tree
2018-02-07 Nikos Nikolerisarch-arm: Fix cache line size for cache maintenace... commit | commitdiff | tree
2018-02-07 Nikos Nikolerisarch-arm: Fault when dc ivac is executed from EL0 commit | commitdiff | tree
2018-02-07 Nikos Nikolerismem-cache: Only pendingModified MSHRs can satisfy CMO... commit | commitdiff | tree
2018-02-07 Nikos Nikolerismem-cache: Cleaned blocks should be marked as not writable commit | commitdiff | tree
2018-02-07 Giacomo Travagliniarch-arm: Change function name for banked miscregs commit | commitdiff | tree
2018-02-07 Giacomo Travagliniarch-arm: Fix AArch32 SETEND Instruction commit | commitdiff | tree
2018-02-07 Giacomo Travagliniarch-arm: Correct Illegal Exception Return detection commit | commitdiff | tree
2018-02-07 Giacomo Travagliniarch-arm: ELUsingAArch32K from armarm pseudocode commit | commitdiff | tree
2018-02-07 Giacomo Travagliniarch-arm: isSecureBelow from armarm pseudocode commit | commitdiff | tree
2018-02-07 Chuan Zhuarch-arm: Fix incorrect assumptions in ELIs64 commit | commitdiff | tree
2018-02-06 Daniel R. Carvalhomem-cache: Remove extra numSets zero check. commit | commitdiff | tree
2018-02-06 Daniel R. Carvalhomem: Standardize mem folder header guards commit | commitdiff | tree
2018-02-05 Gabe Blackbase: Update #includes for bitunion.hh. commit | commitdiff | tree
2018-02-05 Nayan Deshmukhconfig: remove dead code in fs.py commit | commitdiff | tree
2018-02-05 Giacomo Travaglinicpu: MinorCPU handling IsSquashAfter flag commit | commitdiff | tree
2018-02-05 Giacomo Travagliniarch-arm: Removing Serializing flag from ISB commit | commitdiff | tree
2018-02-02 Nikos Nikolerisbase: Fix unused function warning commit | commitdiff | tree
2018-02-01 Sujay Phadkealpha: fix for no 'break' in the case statement commit | commitdiff | tree
2018-02-01 Hanhwi Jangscons: Resolve backtrace implementation existence testi... commit | commitdiff | tree
2018-01-31 Christian Menardarch-x86: consistent style of comments in system files commit | commitdiff | tree
2018-01-30 Maximilian... arch-x86: Granularity bit and segment limit commit | commitdiff | tree
2018-01-29 Gabe Blackriscv: Add overrides to various StaticInst methods. commit | commitdiff | tree
2018-01-29 Gabe Blackbase: Remove the ability to cprintf stringstreams directly. commit | commitdiff | tree
2018-01-29 Gabe Blackbase: Delete commented out versions of the format_integ... commit | commitdiff | tree
2018-01-29 Curtis Dunhamarch-arm: understandably initialize register permissions commit | commitdiff | tree
2018-01-29 Curtis Dunhamarm: extend MiscReg metadata structures commit | commitdiff | tree
2018-01-29 Curtis Dunhamarch-arm: understandably initialize register mappings commit | commitdiff | tree
2018-01-29 Curtis Dunhamconfig, arm: enable device tree autogeneration for... commit | commitdiff | tree
2018-01-29 Glenn Bergmansconfig: Embed Device Tree generation in fs.py config commit | commitdiff | tree
2018-01-29 Glenn Bergmansarm: DT autogeneration - generate PCI node commit | commitdiff | tree
2018-01-29 Glenn Bergmansarm: DT autogeneration - Generate energy controller... commit | commitdiff | tree
2018-01-29 Glenn Bergmansarm: DT autogeneration - autogenerate RealView Platform... commit | commitdiff | tree
2018-01-29 Glenn Bergmansarm: DT autogeneration - Generate memory node commit | commitdiff | tree
2018-01-29 Glenn Bergmansarm: DT autogeneration - Generate cpus node commit | commitdiff | tree
2018-01-29 Glenn Bergmansarm: DT autogeneration - Device Tree generation methods commit | commitdiff | tree
2018-01-29 Glenn Bergmansext: DT autogeneration - Add PyFtd to m5 space commit | commitdiff | tree
2018-01-29 Curtis Dunhamarm: make Arm GenericTimer a ClockedObject commit | commitdiff | tree
2018-01-27 Gabe Blackbase: Add an "override" to name() in the HardBreakpoint... commit | commitdiff | tree
2018-01-27 Gabe Blackbase: Get bitunions to compile on clang 3.8. commit | commitdiff | tree
2018-01-25 Hanhwi Jangutil: Implement Lua module for m5ops. commit | commitdiff | tree
2018-01-23 Swapnil Hariaarch-x86: Adding clflush, clflushopt, clwb instructions commit | commitdiff | tree
2018-01-23 Gabe Blackarch: Remove the "arch/tlb.hh" switching header. commit | commitdiff | tree
2018-01-23 Gabe Blacktarch, mem: Abstract the data stored in the SE page... commit | commitdiff | tree
2018-01-23 Gabe Blackx86, mem: Rewrite the multilevel page table class. commit | commitdiff | tree
2018-01-20 Hanhwi Jangutil: Implement PIC version of m5ops for X86. commit | commitdiff | tree
2018-01-20 Gabe Blackx86, mem: Don't try to force physical addresses on... commit | commitdiff | tree
2018-01-20 Gabe Blackx86, mem: Get rid of PageTableOps::getBasePtr. commit | commitdiff | tree
2018-01-20 Gabe Blackx86, mem: Pass the multi level page table layout in... commit | commitdiff | tree
2018-01-20 Gabe Blackarch, mem: Make the page table lookup function return... commit | commitdiff | tree
2018-01-20 Gabe Blackbase: Hide the BitUnion::__StorageType type. commit | commitdiff | tree
2018-01-20 Gabe Blackarm, base: Generalize and move the BitUnion hash struct. commit | commitdiff | tree
2018-01-20 Gabe Blacksim: Use the new BitUnion templates in serialize.hh. commit | commitdiff | tree
2018-01-20 Gabe Blackbase: Enable specializing templates on BitUnion types. commit | commitdiff | tree
2018-01-20 Gabe Blackbase: Rework bitunions so they can be more flexible. commit | commitdiff | tree
2018-01-20 Gabe Blacksim, arch, base: Refactor the base remote GDB class. commit | commitdiff | tree
2018-01-19 Gabe Blackarch, mem, sim: Consolidate and rename the SE mode... commit | commitdiff | tree
2018-01-18 Andreas Sandbergutil: Add an option to specify paths in list_changes.py commit | commitdiff | tree
2018-01-17 Gabe Blackmem: Change the multilevel page table to inherit from... commit | commitdiff | tree
2018-01-16 Alec Roelkearch-riscv: Fix floating-poing op classes commit | commitdiff | tree
2018-01-16 Alec Roelkearch-riscv: Fix floating-point conversion bugs commit | commitdiff | tree
2018-01-16 Gabe Blacksim: Simplify registerThreadContext a little bit. commit | commitdiff | tree
2018-01-15 Gabe Blackmem: Track TLB entries in the lookup cache as pointers. commit | commitdiff | tree
2018-01-15 Gabe Blackarch: Fix a fatal_if in most of the arch's process... commit | commitdiff | tree
2018-01-12 Xiaoyu Masim: Allow passing a user-defined L2XBar to addTwoLevel... commit | commitdiff | tree
2018-01-11 Earl Ouutil/m5: add Android.mk commit | commitdiff | tree
2018-01-11 Alec Roelkearch-riscv: Don't crash when printing unknown CSRs commit | commitdiff | tree
2018-01-11 Nikos Nikolerismem-ruby: Fix wakeup timeouts for the MOESI_CMP_token... commit | commitdiff | tree
2018-01-11 Nikos Nikolerismem-ruby: Remove function that maps responses to a... commit | commitdiff | tree
2018-01-11 Nikos Nikolerismem-ruby: Add support for multiple DMA engines in MESI_... commit | commitdiff | tree
2018-01-11 Gabe Blackcpu: Make the CPU's TLB parameter a BaseTLB. commit | commitdiff | tree
2018-01-11 Gabe Blackarm, power: Make the python TLB simobjects inherit... commit | commitdiff | tree
2018-01-11 Gabe Blackarch,mem: Remove the default value for page size. commit | commitdiff | tree
2018-01-11 Gabe Blackarch,mem: Move page table construction into the arch... commit | commitdiff | tree
2018-01-10 Chen Zouconfigs: Fill in the cpu.isa field in etrace_replay... commit | commitdiff | tree
2018-01-10 BKPstyle: change C/C++ source permissions to noexec commit | commitdiff | tree
2018-01-10 Alec Roelkearch-riscv: Make use of ImmOp's polymorphism commit | commitdiff | tree
2018-01-10 Gabe Blackalpha,arm,mips,power,riscv,sparc,x86,cpu: Get rid of... commit | commitdiff | tree
2018-01-10 Tuan Taarch-riscv,sim: Support clone syscall in RISC-V commit | commitdiff | tree
2018-01-09 Nikos Nikolerismem-cache: Prune unnecessary writebacks in exclusive... commit | commitdiff | tree
2018-01-09 Hanhwi Jangutil: Add the missing wakecpu m5op in X86. commit | commitdiff | tree
2018-01-09 Hanhwi Jangutil: resolve m5op name mismatching in m5op headers. commit | commitdiff | tree
2018-01-09 Gabe Blackcpu: Use the NotAnInst flag to avoid passing an inst... commit | commitdiff | tree
2018-01-09 Gabe Blackcpu: Add a NotAnInst flag to the BaseDynInst class. commit | commitdiff | tree
2018-01-09 Gabe Blackcpu, power: Get rid of the remnants of the EA computati... commit | commitdiff | tree
2018-01-09 Gabe Blackarm: Make translateFunctional override the base impleme... commit | commitdiff | tree
2018-01-08 Tony Gutierrezgpu-compute: call createThreads() on cpu objs in apu_se.py commit | commitdiff | tree
2018-01-05 Tuan Taarch-riscv: Ignore sched_yield syscall in SE mode commit | commitdiff | tree
2018-01-05 Tuan Tasim: Fix a bug in prlimit syscall in SE mode commit | commitdiff | tree
2018-01-05 Tuan Taarch-riscv: Ignore set_robust_list and get_robust_list... commit | commitdiff | tree
2018-01-05 Tuan Taarch-riscv: Add an implementation of set_tid_address... commit | commitdiff | tree
2018-01-05 Alec Roelkearch-riscv: Correct syscall argument reg count commit | commitdiff | tree
2018-01-04 Alec Roelkearch-riscv: Remove "magic" syscall number constant commit | commitdiff | tree
2018-01-02 Gabe Blackconfig: Handle NULL simobject parameters in read_config.py. commit | commitdiff | tree
2018-01-02 Gabe Blackconfig: Fix parsing AddrRange parameters in read_config.py. commit | commitdiff | tree
2018-01-02 Gabe Blackconfig: Add a --checkpoint-dir argument to read_config.py. commit | commitdiff | tree
2017-12-23 Gabe Blackalpha,arm,mips,power,riscv,sparc,x86: Get rid of TheISA... commit | commitdiff | tree
2017-12-23 Gabe Blackriscv,x86: Stop using the arch Nop machine instruction... commit | commitdiff | tree
2017-12-22 Gabe Blackarch,cpu: "virtualize" the TLB interface. commit | commitdiff | tree
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