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yosys.git
2020-08-01
Zachary Snow
Fix generate scoping issues
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2020-07-31
Claire Wolf
Bump YOSYS_VER
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2020-07-30
Marcelina Kościelnicka
Add dffunmap pass.
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2020-07-30
Marcelina Kościelnicka
opt_expr: Remove -clkinv option, make it the default.
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2020-07-30
Marcelina Kościelnicka
synth_ice40: Use opt_dff.
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2020-07-30
Marcelina Kościelnicka
synth_xilinx: Use opt_dff.
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2020-07-30
Marcelina Kościelnicka
async2sync: Support all FF types.
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2020-07-30
Marcelina Kościelnicka
Add opt_dff pass.
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2020-07-30
Marcelina Kościelnicka
verilog_backend: Add handling for all FF types.
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2020-07-29
Miodrag Milanović
Merge pull request #2314 from YosysHQ/verifix_errorfix
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2020-07-29
Miodrag Milanovic
Clear last error message
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2020-07-29
Marcelina Kościelnicka
opt_expr: Fix handling of $_XNOR_ cells with A = B.
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2020-07-28
Marcelina Kościelnicka
ffinit: Fortify the code a bit.
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2020-07-28
clairexen
Merge pull request #2301 from zachjs/for-loop-errors
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2020-07-28
clairexen
Merge pull request #2306 from YosysHQ/mwk/equiv_induct...
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2020-07-27
Marcelina Kościelnicka
equiv_induct: Fix up assumption for $equiv cells in...
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2020-07-27
Dan Ravensloft
intel_alm: direct M10K instantiation
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2020-07-26
Dan Ravensloft
intel_alm: increase abc9 -W
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2020-07-26
clairexen
Merge pull request #2299 from zachjs/arg-loop
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2020-07-25
Zachary Snow
Clearer for loop error messages
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2020-07-25
Zachary Snow
Avoid generating wires for function args which are...
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2020-07-24
Marcelina Kościelnicka
async2sync: Refactor to use FfInitVals.
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2020-07-24
Marcelina Kościelnicka
memory_dff: Refactor to use FfInitVals.
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2020-07-24
Marcelina Kościelnicka
proc_dlatch: Refactor to use FfInitVals.
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2020-07-24
Marcelina Kościelnicka
pmux2shift: Refactor to use FfInitVals.
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2020-07-24
Marcelina Kościelnicka
wreduce: Refactor to use FfInitVals.
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2020-07-24
Marcelina Kościelnicka
techmap: Refactor to use FfInitVals.
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2020-07-24
Marcelina Kościelnicka
shregmap: Refactor to use FfInitVals.
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2020-07-24
Marcelina Kościelnicka
abc: Refactor to use FfInitVals.
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2020-07-24
Marcelina Kościelnicka
dffinit: Refactor to use FfInitVals.
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2020-07-24
Marcelina Kościelnicka
zinit: Refactor to use FfInitVals.
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2020-07-24
Marcelina Kościelnicka
dfflegalize: Refactor to use FfInitVals.
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2020-07-24
Marcelina Kościelnicka
clk2fflogic: Support all FF types.
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2020-07-24
Marcelina Kościelnicka
satgen: Add support for dffe, sdff, sdffe, sdffce cells.
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2020-07-23
Marcelina Kościelnicka
Add utility module for representing flip-flops.
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2020-07-23
Marcelina Kościelnicka
memory_dff: recognize more dff cells
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2020-07-23
Marcelina Kościelnicka
Add utility module for dealing with init attributes.
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2020-07-23
clairexen
Merge pull request #2285 from YosysHQ/mwk/techmap-cellname
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2020-07-23
clairexen
Merge pull request #2294 from Ravenslofty/intel_alm_timings
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2020-07-23
Dan Ravensloft
intel_alm: add additional ABC9 timings
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2020-07-22
Keith Rothman
Remove EXPLICIT_CARRY logic.
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2020-07-21
Marcelina Kościelnicka
techmap: Add _TECHMAP_CELLNAME_ special parameter.
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2020-07-21
clairexen
Merge pull request #2215 from boqwxp/qbfsat-solver...
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2020-07-20
Alberto Gonzalez
smtio: Emit `mode: start` options before `set-logic...
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2020-07-20
Alberto Gonzalez
smtio: Add support for parsing `yosys-smt2-solver-optio...
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2020-07-20
Alberto Gonzalez
qbfsat: Add `-solver-option` option.
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2020-07-20
Alberto Gonzalez
smt2: Add `-solver-option` option.
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2020-07-20
clairexen
Merge pull request #2282 from YosysHQ/claire/satunsat
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2020-07-20
Marcelina Kościelnicka
celltypes: Fix EN port name for some FF types.
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2020-07-20
Claire Wolf
Only allow "sat" and "unsat" smt solver responses in...
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2020-07-20
clairexen
Merge pull request #2276 from YosysHQ/mwk/satgen-cc
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2020-07-18
Marcelina Kościelnicka
satgen: Move importCell out of the header.
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2020-07-17
Miodrag Milanović
Merge pull request #2275 from YosysHQ/mwk/sf2-clkint-fix
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2020-07-17
Marcelina Kościelnicka
sf2: Emit CLKINT even if -clkbuf not passed
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2020-07-17
Miodrag Milanović
Merge pull request #2274 from YosysHQ/mwk/anlogic-ff-fix
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2020-07-17
Marcelina Kościelnicka
anlogic: Fix FF mapping.
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2020-07-16
clairexen
Merge pull request #2229 from Ravenslofty/sf2_remove_sf...
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2020-07-16
clairexen
Merge pull request #2273 from whitequark/write-verilog...
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2020-07-16
clairexen
Merge pull request #2272 from whitequark/write-verilog-sv
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2020-07-16
Miodrag Milanović
Merge pull request #2238 from YosysHQ/mwk/dfflegalize...
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2020-07-16
Miodrag Milanović
Merge pull request #2226 from YosysHQ/mwk/nuke-efinix...
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2020-07-16
whitequark
verilog_backend: in non-SV mode, add a trigger for...
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2020-07-16
whitequark
verilog_backend: add `-sv` option, make `-o <filename...
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2020-07-16
whitequark
Merge pull request #2270 from whitequark/cxxrtl-fix...
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2020-07-15
whitequark
Merge pull request #2269 from YosysHQ/claire/bisonwall
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2020-07-15
Claire Wolf
Treat all bison warnings as errors in verilog front-end
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2020-07-15
Claire Wolf
Use %precedence in verilog_parser.y
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2020-07-15
Claire Wolf
Fix bison warnings for missing %empty
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2020-07-15
Claire Wolf
Run bison with -Wall for verilog front-end
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2020-07-15
clairexen
Merge pull request #2257 from antmicro/fix-conflicts
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2020-07-15
Kamil Rakoczy
Add missing semicolons
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2020-07-15
Marcelina Kościelnicka
opt_merge: Dedup one more use of FF cell type list.
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2020-07-14
Marcelina Kościelnicka
achronix: Use dfflegalize.
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2020-07-14
whitequark
cxxrtl: fix typo. NFC.
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2020-07-14
Marcelina Kościelnicka
anlogic: Use dfflegalize.
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2020-07-13
Marcelina Kościelnicka
intel: Use dfflegalize.
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2020-07-13
Lofty
Revert "intel_alm: direct M10K instantiation"
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2020-07-13
whitequark
Merge pull request #2263 from whitequark/cxxrtl-capi...
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2020-07-12
whitequark
cxxrtl: expose eval() and commit() via the C API.
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2020-07-12
Marcelina Kościelnicka
xilinx: Fix srl regression.
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2020-07-12
Marcelina Kościelnicka
proc_dlatch: Remove init values for combinatorial proce...
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2020-07-12
Marcelina Kościelnicka
dfflegalize: Gather init values from all wires.
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2020-07-10
clairexen
Merge pull request #2256 from YosysHQ/claire/fix2241
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2020-07-10
Claire Wolf
Add AST_EDGE support to AstNode::detect_latch(), fixes...
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2020-07-10
Kamil Rakoczy
Fix S/R conflicts
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2020-07-10
Kamil Rakoczy
Fix R/R conflicts
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2020-07-10
Kamil Rakoczy
Revert "Revert PRs #2203 and #2244."
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2020-07-09
Dan Ravensloft
sf2: replace sf2_iobs with {clkbuf,iopad}map
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2020-07-09
whitequark
Merge pull request #2255 from whitequark/bison-Werror...
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2020-07-09
whitequark
Merge pull request #2254 from whitequark/cxxrtl-extern-c
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2020-07-09
Marcelina Kościelnicka
sf2: Use dfflegalize.
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2020-07-09
whitequark
verilog_parser: turn S/R and R/R conflicts into hard...
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2020-07-09
whitequark
Revert PRs #2203 and #2244.
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2020-07-09
whitequark
cxxrtl: add missing extern "C".
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2020-07-09
Marcelina Kościelnicka
xilinx: Use dfflegalize.
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2020-07-09
Marcelina Kościelnicka
dfflibmap: Refactor to use dfflegalize internally.
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2020-07-09
Lucas Castro
Fix issue #2251 (#2252)
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2020-07-09
Marcelina Kościelnicka
clkbufmap: improve input pad handling.
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2020-07-09
clairexen
Merge pull request #2244 from antmicro/logic
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2020-07-09
Marcelina Kościelnicka
clk2fflogic: Consistently treat async control signals...
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