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yosys.git
2019-08-06
David Shah
[wip] DSP48E1 sim model improvements
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2019-08-06
David Shah
[wip] DSP48E1 sim model improvements
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2019-08-01
Eddie Hung
Add comment about supporting $dffe in ice40_dsp
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2019-08-01
Eddie Hung
Pack P register properly
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2019-08-01
Eddie Hung
Trim Y_WIDTH
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2019-08-01
Eddie Hung
Add DSP_SIGNEDONLY back
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2019-08-01
Eddie Hung
DSP_MINWIDTH -> DSP_{A,B,Y}_MINWIDTH
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2019-08-01
Eddie Hung
Change $__softmul back to $mul
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2019-08-01
Eddie Hung
Cope with sign extension in mul2dsp
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2019-08-01
Eddie Hung
Revert "Do not do sign extension in techmap; let packer...
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2019-08-01
Eddie Hung
Merge remote-tracking branch 'origin/master' into xc7dsp
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2019-08-01
Eddie Hung
Fix B_WIDTH > DSP_B_MAXWIDTH case
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2019-08-01
Eddie Hung
CO is sign extension only if signed multiplier
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2019-08-01
Eddie Hung
Fix typo
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2019-08-01
Eddie Hung
Merge pull request #1236 from YosysHQ/eddie/xc6s_brams_map
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2019-07-31
Eddie Hung
Do not compute sign bit if result is zero
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2019-07-31
Eddie Hung
For signed multipliers, compute sign bit separately...
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2019-07-31
Eddie Hung
Restore old CO behaviour
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2019-07-31
Eddie Hung
Helper: SigSpec::operator[] to accept negative indices
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2019-07-31
Clifford Wolf
Merge pull request #1233 from YosysHQ/clifford/defer
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2019-07-29
Eddie Hung
RST -> RSTBRST for RAMB8BWER
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2019-07-29
Eddie Hung
Merge pull request #1228 from YosysHQ/dave/yy_buf_size
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2019-07-29
David Shah
Merge pull request #1234 from mmicko/fix_gzip_no_exist
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2019-07-29
Miodrag Milanovic
Fix case when file does not exist
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2019-07-29
Clifford Wolf
Update README to use "read" instead of "read_verilog"
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2019-07-29
Clifford Wolf
Call "read_verilog" with -defer from "read"
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2019-07-27
David Shah
Merge pull request #1226 from YosysHQ/dave/gzip
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2019-07-26
Eddie Hung
Fix spacing
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2019-07-26
Eddie Hung
Update test_autotb doc to reflect default value of...
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2019-07-26
Eddie Hung
Add doc for "test_autotb -seed" option
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2019-07-26
Eddie Hung
Pop the CO bit from O
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2019-07-26
Eddie Hung
Allow adders/accumulators with 33 bits using CO output
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2019-07-26
David Shah
Update CHANGELOG
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2019-07-26
David Shah
verilog_lexer: Increase YY_BUF_SIZE to 65536
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2019-07-26
David Shah
Fix frontend auto-detection for gzipped input
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2019-07-26
David Shah
Add support for reading gzip'd input files
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2019-07-25
Eddie Hung
Merge branch 'master' of github.com:YosysHQ/yosys
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2019-07-25
Eddie Hung
Bump abc to fix &mfs bug
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2019-07-25
Clifford Wolf
Merge branch 'ZirconiumX-synth_intel_m9k'
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2019-07-25
Clifford Wolf
Merge pull request #1218 from ZirconiumX/synth_intel_iopads
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2019-07-25
Clifford Wolf
Merge pull request #1219 from jakobwenzel/objIterator
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2019-07-25
Eddie Hung
Merge pull request #1224 from YosysHQ/xilinx_fix_ff
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2019-07-25
Jakob Wenzel
replaced std::iterator with using statements
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2019-07-25
David Shah
xilinx: Fix missing cell name underscore in cells_map.v
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2019-07-24
Eddie Hung
Merge pull request #1222 from koriakin/s6-example
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2019-07-24
Eddie Hung
Add copyright header, comment on cascade
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2019-07-24
Marcin KoĆcielnicki
Add a simple example for Spartan 6
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2019-07-24
Jakob Wenzel
made ObjectIterator extend std::iterator
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2019-07-24
Dan Ravensloft
intel: Make -noiopads the default
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2019-07-23
Eddie Hung
Eliminate warnings by sizing O correctly
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2019-07-23
Eddie Hung
Typo for Y_WIDTH
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2019-07-23
Eddie Hung
Fix muxAB logic
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2019-07-23
Eddie Hung
Remove debug print
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2019-07-23
Eddie Hung
Simplify and fix for MACs
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2019-07-23
Eddie Hung
Fix typo
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2019-07-23
Dan Ravensloft
intel: Map M9K BRAM only on families that have it
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2019-07-23
Eddie Hung
Merge pull request #1212 from YosysHQ/eddie/signed_ice4...
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2019-07-22
Eddie Hung
Fix spacing
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2019-07-22
Eddie Hung
Remove debug
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2019-07-22
Eddie Hung
Pack hi and lo registers separately
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2019-07-22
Eddie Hung
SigSpec::extract() to return as many bits as poss if...
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2019-07-22
Eddie Hung
Rename according to vendor doc TN1295
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2019-07-22
Eddie Hung
Pack Y register
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2019-07-22
Eddie Hung
opt and wreduce necessary for -dsp
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2019-07-22
Eddie Hung
Pack adders not just accumulators
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2019-07-22
Eddie Hung
Use minimum sized width wires
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2019-07-22
Eddie Hung
Merge pull request #1214 from jakobwenzel/astmod_clone
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2019-07-22
Jakob Wenzel
initialize noblackbox and nowb in AstModule::clone
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2019-07-20
Clifford Wolf
Add "stat -tech cmos"
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2019-07-20
Eddie Hung
Restore old ffY behaviour
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2019-07-20
Eddie Hung
Cleanup
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2019-07-20
Eddie Hung
Indirection via $__soft_mul
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2019-07-19
Eddie Hung
Do not do sign extension in techmap; let packer do it
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2019-07-19
Eddie Hung
Merge remote-tracking branch 'origin/eddie/wreduce_add...
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2019-07-19
Eddie Hung
Add another test
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2019-07-19
Eddie Hung
Do not access beyond bounds
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2019-07-19
Eddie Hung
Add an SigSpec::at(offset, defval) convenience method
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2019-07-19
Eddie Hung
Wrap A and B in sigmap
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2019-07-19
Eddie Hung
Remove "top" from message
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2019-07-19
Eddie Hung
Merge remote-tracking branch 'origin/eddie/wreduce_add...
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2019-07-19
Eddie Hung
Also optimise MSB of $sub
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2019-07-19
Eddie Hung
Add one more test with trimming Y_WIDTH of $sub
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2019-07-19
Eddie Hung
Be more explicit
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2019-07-19
Eddie Hung
wreduce for $sub
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2019-07-19
Eddie Hung
Add tests for sub too
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2019-07-19
Eddie Hung
Add test
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2019-07-19
Eddie Hung
SigSpec::extract to take negative lengths
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2019-07-19
Eddie Hung
Do not $mul -> $__mul if A and B are less than maxwidth
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2019-07-19
Eddie Hung
Add DSP_MINWIDTH=11 for ice40 since ice40_dsp uses...
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2019-07-19
Eddie Hung
Add a DSP_MINWIDTH macro, and soft-logic for {A_WIDTH...
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2019-07-19
Eddie Hung
Fine tune ice40_dsp.pmg, add support for packing subset...
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2019-07-19
Eddie Hung
Add support for ice40 signed multipliers
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2019-07-19
Eddie Hung
Merge branch 'xc7dsp' into ice40dsp
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2019-07-19
Eddie Hung
Fix typo in B
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2019-07-19
Eddie Hung
Merge remote-tracking branch 'origin/eddie/signed_ice40...
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2019-07-19
David Shah
ice40: Fix test_dsp_model.sh
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2019-07-19
David Shah
ice40/cells_sim.v: Fix sign of J and K partial products
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2019-07-19
Eddie Hung
Use sign_headroom instead
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2019-07-19
David Shah
ice40/cells_sim.v: LSB of A/B only signed in 8x8 mode
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2019-07-19
Eddie Hung
Add tests for all combinations of A and B signedness...
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