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riscv-isa-sim.git
2016-05-23
Tim Newsome
Do a better job checking CSR functionality.
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2016-05-23
Tim Newsome
Rename gdbserver-smoke.py to gdbserver.py.
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2016-05-23
Tim Newsome
Test 'info registers all' as well as 'info all-registers'
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2016-05-23
Tim Newsome
Minor cleanup.
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2016-05-23
Tim Newsome
Update regnum handling to match gdb CSR changes.
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2016-05-23
Tim Newsome
Forgot to add this source.
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2016-05-23
Tim Newsome
Treat warnings as errors.
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2016-05-23
Tim Newsome
Implement register writes.
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2016-05-23
Tim Newsome
Properly clean up spike.
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2016-05-23
Tim Newsome
Implement reading of CSRs.
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2016-05-23
Tim Newsome
Add some tests that pass and test something.
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2016-05-23
Tim Newsome
Flush icache when using swbps and report to gdb.
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2016-05-23
Tim Newsome
Add very basic 'make check'.
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2016-05-23
Tim Newsome
Make 'make check' not hang forever.
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2016-05-23
Tim Newsome
Software breakpoints seem to work.
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2016-05-23
Tim Newsome
Rewrite GPL'd code from OpenOCD.
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2016-05-23
Tim Newsome
Looks like single step works.
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2016-05-23
Tim Newsome
Add -H to start halted.
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2016-05-23
Tim Newsome
Implement binary memory write.
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2016-05-23
Tim Newsome
Now you can halt/continue from gdb.
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2016-05-23
Tim Newsome
Register read looks sane now.
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2016-05-23
Tim Newsome
gdb can now read spike memory.
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2016-05-23
Tim Newsome
Hack to the point where gdb reads a register.
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2016-05-23
Tim Newsome
Listen on a socket for gdb to connect to.
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2016-05-22
Andrew Waterman
Allow delegation of device interrupts
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2016-05-21
Garret Kelly
htif: catch proper store exception (#44)
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2016-05-21
Andy Wright
Some bugfixes for CSR reading and setting FS for fflags...
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2016-05-19
Tim Newsome
Merge pull request #42 from csail-csg/master
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2016-05-19
acw1251
Removed devicetree.h from riscv.mk.in since it no longe...
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2016-05-18
acw1251
Added missing header files to riscv.mk.in
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2016-05-02
Andrew Waterman
Add back IPI support
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2016-05-02
Andrew Waterman
Remove MIPI; mip.MSIP bit is read-only
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2016-05-02
Andrew Waterman
Remove tohost/fromhost registers
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2016-05-01
Andrew Waterman
Initialize mtvec to DEFAULT_MTVEC
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2016-05-01
Andrew Waterman
Remove SCRs; add padding after config string
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2016-04-29
Andrew Waterman
Move much closer to new platform-M memory map
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2016-04-28
Andrew Waterman
Add --dump-config-string flag
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2016-04-28
Andrew Waterman
Remove MTIME[CMP]; add RTC device
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2016-04-20
Andrew Waterman
Split ERET into URET, SRET, HRET, MRET
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2016-04-06
Andrew Waterman
Remove non-standard uarch CSRs
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2016-04-03
Andrew Waterman
Allow configuration of default ISA with --with-isa
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2016-03-17
Andrew Waterman
Update definition of base field in misa register
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2016-03-04
Andrew Waterman
Fix up interrupt delegation
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2016-03-02
Andrew Waterman
Add counter-enable registers
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2016-03-02
Andrew Waterman
Use RV config string rather than FDT
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2016-03-02
Andrew Waterman
WIP on priv spec v1.9
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2016-03-02
Andrew Waterman
New definitions of misa/marchid/mvendorid
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2016-03-02
Andrew Waterman
implement PUM functionality
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2016-03-02
Andrew Waterman
sptbr now a holds a PPN, not an address
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2016-03-02
Andrew Waterman
Return to interactive mode after a trap
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2016-03-02
Andrew Waterman
Use simpler MTVEC scheme
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2016-03-02
Andrew Waterman
Fix ERET bug
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2016-03-02
Andrew Waterman
Zero-extend all CSR writes
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2016-03-02
Andrew Waterman
Fix ERET serialization strategy
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2016-03-02
Andrew Waterman
Add autoconf check for little-endianness
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2016-03-02
Andrew Waterman
Set default RV32 RAM size to 4 GiB - 256 MiB
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2016-03-02
Andrew Waterman
Serialize simulator on ERET
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2016-03-02
Andrew Waterman
WIP on priv spec v1.9
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2016-03-02
Andrew Waterman
Compile debug symbols
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2016-03-02
Andrew Waterman
Mark SoftFloat routines static inline
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2016-03-02
Andrew Waterman
Upgrade to latest SoftFloat
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2016-02-04
Andrew Waterman
Actually refill ITLB on ITLB miss
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2016-01-30
Andrew Waterman
Fix NaN propagation for fcvt
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2016-01-24
Andrew Waterman
Remove hwacha support
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2016-01-13
Andrew Waterman
Use new NaN discipline
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2016-01-13
Andrew Waterman
don't ignore data value when writing MIPI
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2016-01-05
Andrew Waterman
fix help message
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2015-12-17
Scott Beamer
another osx clang compatability fix
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2015-11-20
Andrew Waterman
C.ADDIW is reserved for rd=0
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2015-11-13
Andrew Waterman
Generate device tree for target machine
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2015-11-13
Andrew Waterman
Access FP regs through a macro
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2015-11-05
Andrew Waterman
Merge pull request #34 from zizztux/incorrect_int_reg_count
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2015-10-28
SeungRyeol Lee
Fix incorrect upper limit for loop on interactive int...
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2015-10-26
Andrew Waterman
Fix histogram for RVC
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2015-10-20
Andrew Waterman
Update to hopefully final RVC 1.9 encoding
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2015-10-13
Andrew Waterman
Fix --dc flag
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2015-10-06
Andrew Waterman
RVC encoding tweak
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2015-10-06
Andrew Waterman
more work towards RVC 1.8
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2015-10-02
Andrew Waterman
work towards rvc 1.8
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2015-10-02
Andrew Waterman
clean up shift instruction implementation
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2015-09-25
Andrew Waterman
Refactor memory access code; add MMIO support
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2015-09-25
Andrew Waterman
Use enum instead of two bools to denote memory access...
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2015-09-16
Scott Beamer
commit log now correctly prints privilege
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2015-09-15
Christopher...
Zero-extend flw, fmv_s_x instructions
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2015-09-12
Scott Beamer
print out current privilege level (if commit log enabled)
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2015-09-12
Scott Beamer
print out commit log (if enabled) for all privilege...
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2015-09-11
Andrew Waterman
Simplify register_base_instructions
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2015-09-11
Andrew Waterman
Initialize mstatus.prv1/prv2 to U, not S
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2015-09-11
Andrew Waterman
Support 'G' in ISA strings
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2015-09-11
Andrew Waterman
Merge pull request #32 from riscv/insn-list
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2015-09-11
Albert Ou
Fix non-portable sed commands generating insn_list.h
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2015-09-09
Andrew Waterman
Improve instruction fetch
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2015-09-08
Andrew Waterman
Add facility to instrument specific opcodes
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2015-09-08
Andrew Waterman
Refer to LICENSE in some newer source files
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2015-09-04
Andrew Waterman
Move towards RVC v1.8
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2015-09-02
Andrew Waterman
Don't automatically run autoconf
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2015-08-06
Andrew Waterman
Merge pull request #29 from pmundkur/devel
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2015-08-06
Prashanth Mundkur
Add an option (-l) to display a log of execution in...
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2015-07-30
Christopher...
Added error message when trying to use histogram
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2015-07-21
Christopher...
Update README.md for freg info
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