yosys.git
2019-07-24 Jim LawsonMerge remote-tracking branch 'upstream/master'
2019-07-23 Eddie HungMerge pull request #1212 from YosysHQ/eddie/signed_ice4...
2019-07-22 Eddie HungMerge pull request #1214 from jakobwenzel/astmod_clone
2019-07-22 Jakob Wenzelinitialize noblackbox and nowb in AstModule::clone
2019-07-20 Clifford WolfAdd "stat -tech cmos"
2019-07-19 David Shahice40: Fix test_dsp_model.sh
2019-07-19 David Shahice40/cells_sim.v: Fix sign of J and K partial products
2019-07-19 David Shahice40/cells_sim.v: LSB of A/B only signed in 8x8 mode
2019-07-19 Eddie HungAdd tests for all combinations of A and B signedness...
2019-07-19 Eddie HungDon't copy ref if exists already
2019-07-18 David ShahMerge pull request #1208 from ZirconiumX/intel_cleanups
2019-07-18 Dan Ravensloftsynth_intel: Use stringf
2019-07-18 David ShahMerge pull request #1207 from ZirconiumX/intel_new_pass...
2019-07-18 Dan Ravensloftsynth_intel: s/not family/no family/
2019-07-18 Dan Ravensloftsynth_intel: revert change to run_max10
2019-07-18 Ben Widawskyintel_synth: Fix help message
2019-07-18 Ben Widawskyintel_synth: Small code cleanup to remove if ladder
2019-07-18 Ben Widawskyintel_synth: Make family explicit and match
2019-07-18 Ben Widawskyintel_synth: Minor code cleanups
2019-07-18 Dan Ravensloftsynth_intel: rename for consistency with #1184
2019-07-18 Clifford WolfMerge pull request #1184 from whitequark/synth-better...
2019-07-18 Clifford WolfMerge pull request #1203 from whitequark/write_verilog...
2019-07-17 Clifford WolfRemove old $pmux_safe code from write_verilog
2019-07-17 David ShahMerge pull request #1204 from smunaut/fix_1187
2019-07-16 Sylvain Munautice40: Adapt the relut process passes to the new $lut...
2019-07-16 whitequarkwrite_verilog: dump zero width constants correctly.
2019-07-16 Eddie HungMerge pull request #1202 from YosysHQ/cmp2lut_lut6
2019-07-16 whitequarksynth_ecp5: rename dram to lutram everywhere.
2019-07-16 whitequarksynth_{ice40,ecp5}: more sensible pass label naming.
2019-07-16 Eddie Hunggen_lut to return correctly sized LUT mask
2019-07-16 Eddie HungForgot to commit
2019-07-16 Eddie HungAdd tests for cmp2lut on LUT6
2019-07-16 Eddie HungMerge pull request #1188 from YosysHQ/eddie/abc9_push_i...
2019-07-16 Eddie HungMerge pull request #1186 from YosysHQ/eddie/abc9_ice40_fix
2019-07-16 Clifford WolfMerge pull request #1200 from mmicko/fix_typo_liberty_cc
2019-07-16 Clifford WolfMerge pull request #1199 from mmicko/extract_fa_fix
2019-07-16 Miodrag MilanovicFix typo, double "of"
2019-07-16 Miodrag MilanovicFix check logic in extract_fa
2019-07-15 Eddie HungMerge pull request #1196 from YosysHQ/eddie/fix1178
2019-07-15 Eddie Hung$__ICE40_CARRY_LUT4 -> $__ICE40_FULL_ADDER as per ...
2019-07-15 Clifford WolfMerge pull request #1189 from YosysHQ/eddie/fix1151
2019-07-15 Clifford WolfMerge pull request #1190 from YosysHQ/eddie/fix_1099
2019-07-15 Clifford WolfMerge pull request #1191 from whitequark/opt_lut-log_debug
2019-07-15 Clifford WolfMerge pull request #1195 from Roman-Parise/master
2019-07-15 Clifford WolfMerge pull request #1197 from nakengelhardt/handle...
2019-07-15 Eddie HungRevert "Add log_checkpoint function and use it in opt_m...
2019-07-15 N. Engelhardtsmt: handle failure of setrlimit syscall
2019-07-15 Eddie HungRevert "Fix first divergence in #1178"
2019-07-15 Eddie HungMerge branch 'master' into eddie/fix1178
2019-07-15 Clifford WolfRedesign log_id_cache so that it doesn't keep IdString...
2019-07-15 Clifford WolfAdd log_checkpoint function and use it in opt_muxtree
2019-07-14 Eddie HungMerge pull request #1194 from cr1901/miss-semi
2019-07-14 William D.... Fix missing semicolon in Windows-specific code in aiger...
2019-07-14 Roman-PariseUpdated FreeBSD dependencies in README.md
2019-07-13 whitequarkopt_lut: make less chatty.
2019-07-13 Eddie HungIf ConstEval fails do not log_abort() but return gracefully
2019-07-13 Eddie HungError out if enable > dbits
2019-07-13 Eddie Hungice40_opt to $__ICE40_CARRY_LUT4 into $lut not SB_LUT
2019-07-13 Eddie HungAdd comment
2019-07-13 Eddie HungUpdate test with more accurate LUT mask
2019-07-13 Eddie Hungduplicate -> clone
2019-07-13 Eddie HungMore cleanup
2019-07-13 Eddie HungCleanup
2019-07-13 Eddie HungCleanup
2019-07-13 Eddie HungCleanup
2019-07-13 Eddie HungMore cleanup
2019-07-13 Eddie HungCleanup
2019-07-13 Eddie HungCleanup
2019-07-13 Eddie HungCleanup
2019-07-12 Eddie HungDo not double count cells in abc
2019-07-12 Clifford WolfMerge pull request #1183 from whitequark/ice40-always...
2019-07-12 Eddie HungUse Const::from_string() not its constructor...
2019-07-12 Eddie HungOff by one
2019-07-12 Eddie HungFix spacing
2019-07-12 Eddie HungRemove double push
2019-07-12 Eddie HungMap to and from this box if -abc9
2019-07-12 Eddie Hungice40_opt to handle this box and opt back to SB_LUT4
2019-07-12 Eddie HungAdd new box to cells_sim.v
2019-07-12 Eddie Hung_ABC macro will map and unmap to this new box
2019-07-12 Eddie HungCombine SB_CARRY+SB_LUT into one $__ICE40_CARRY_LUT4 box
2019-07-11 whitequarksynth_ice40: switch -relut to be always on.
2019-07-11 whitequarksynth_ice40: fix help text typo. NFC.
2019-07-11 Eddie HungMerge pull request #1182 from koriakin/xc6s-bram
2019-07-11 Eddie HungMerge pull request #1185 from koriakin/xc-ff-init-vals
2019-07-11 Marcin Kościelnickixilinx: Fix the default values for FDPE/FDSE INIT attri...
2019-07-11 Eddie HungEnable &mfs for abc9, even if it only currently works...
2019-07-11 Marcin Kościelnickisynth_xilinx: Initial Spartan 6 block RAM inference...
2019-07-11 Clifford WolfMerge pull request #1172 from whitequark/write_verilog...
2019-07-11 Clifford WolfMerge pull request #1179 from whitequark/attrmap-proc
2019-07-10 Eddie HungMerge pull request #1180 from YosysHQ/eddie/no_abc9_retime
2019-07-10 Eddie HungMerge pull request #1148 from YosysHQ/xc7mux
2019-07-10 Eddie HungError out if -abc9 and -retime specified
2019-07-10 Eddie HungAdd some spacing
2019-07-10 Eddie HungAdd some ASCII art explaining mux decomposition
2019-07-10 whitequarkattrmap: also consider process, switch and case attributes.
2019-07-10 Clifford WolfMerge pull request #1177 from YosysHQ/clifford/async
2019-07-10 Eddie HungCall muxpack and pmux2shiftx before cmp2lut
2019-07-09 Eddie HungFix first divergence in #1178
2019-07-09 Eddie HungRestore opt_clean back to original place
2019-07-09 Eddie HungRestore missing techmap -map +/cmp2lut.v with LUT_WIDTH=6
next