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yosys.git
2019-04-13
Eddie Hung
Merge branch 'xaig' of github.com:YosysHQ/yosys into...
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2019-04-13
Eddie Hung
Fix inout handling for -map option
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2019-04-12
Eddie Hung
Merge branch 'xaig' of github.com:YosysHQ/yosys into...
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2019-04-12
Eddie Hung
Merge remote-tracking branch 'origin/master' into xaig
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2019-04-12
Eddie Hung
Use -map instead of -symbols for aiger
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2019-04-12
Eddie Hung
ci_bits and co_bits now a list, order is important...
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2019-04-12
Eddie Hung
Also cope with duplicated CIs
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2019-04-12
Eddie Hung
WIP
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2019-04-12
Eddie Hung
Comment out
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2019-04-12
Eddie Hung
Add support for synth_xilinx -abc9 and ignore abc9...
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2019-04-12
Eddie Hung
Cope with an output having same name as an input (i...
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2019-04-12
Eddie Hung
Merge remote-tracking branch 'origin/master' into xaig
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2019-04-12
Eddie Hung
Merge pull request #928 from litghost/add_xc7_sim_models
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2019-04-12
Keith Rothman
Remove BUFGCTRL, BUFHCE and LUT6_2 from cells_xtra.
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2019-04-12
Clifford Wolf
Merge pull request #933 from dh73/master
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2019-04-12
Clifford Wolf
Merge pull request #932 from YosysHQ/eddie/fixdlatch
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2019-04-12
Diego
Fixing issues in CycloneV cell sim
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2019-04-11
Eddie Hung
Add default entry to testcase
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2019-04-11
Eddie Hung
Recognise default entry in case even if all cases cover...
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2019-04-11
Eddie Hung
Add non-input bits driven by unrecognised cells as...
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2019-04-10
Eddie Hung
parse_aiger() to rename all $lut cells after "clean"
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2019-04-09
Keith Rothman
Fix LUT6_2 definition.
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2019-04-09
Keith Rothman
Add additional cells sim models for core 7-series prima...
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2019-04-08
Eddie Hung
Fix a few typos
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2019-04-08
Eddie Hung
More space fixing
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2019-04-08
Eddie Hung
Fix spacing
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2019-04-08
Eddie Hung
Merge branch 'master' into xaig
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2019-04-08
Clifford Wolf
Merge pull request #919 from YosysHQ/multiport_transp
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2019-04-07
David Shah
memory_bram: Fix multiport make_transp
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2019-04-05
Clifford Wolf
Add "read_ilang -lib"
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2019-04-04
Clifford Wolf
Added missing argument checking to "mutate" command
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2019-04-03
Eddie Hung
Merge pull request #913 from smunaut/fix_proc_mux
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2019-04-03
Sylvain Munaut
proc_mux: Fix crash when trying to optimize non-existan...
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2019-04-03
Clifford Wolf
Merge pull request #912 from YosysHQ/bram_addr_en
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2019-04-03
Clifford Wolf
Merge pull request #910 from ucb-bar/memupdates
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2019-04-02
David Shah
memory_bram: Consider read enable for address expansion...
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2019-04-02
Eddie Hung
Merge pull request #895 from YosysHQ/pmux2shiftx
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2019-04-01
Jim Lawson
Refine memory support to deal with general Verilog...
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2019-03-29
Clifford Wolf
Merge pull request #907 from YosysHQ/clifford/fix906
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2019-03-29
Clifford Wolf
Build Verilog parser with -DYYMAXDEPTH=100000, fixes...
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2019-03-28
Clifford Wolf
Merge pull request #901 from trcwm/libertyfixes
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2019-03-28
Clifford Wolf
Merge pull request #903 from YosysHQ/bram_reset_transp
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2019-03-27
David Shah
memory_bram: Reset make_transp when growing read ports
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2019-03-27
Niels Moseley
Liberty file parser now accepts superfluous ;
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2019-03-27
Niels Moseley
Liberty file parser now accepts superfluous ;
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2019-03-27
Niels Moseley
Liberty file parser now accepts superfluous ;
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2019-03-27
Clifford Wolf
Add "read -verific" and "read -noverific"
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2019-03-27
Clifford Wolf
Add "rename -output"
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2019-03-27
Clifford Wolf
Improve "rename" help message
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2019-03-26
Clifford Wolf
Add "cutpoint -undef"
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2019-03-26
Clifford Wolf
Add "hdlname" attribute
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2019-03-26
Clifford Wolf
Fix "verific -extnets" for more complex situations
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2019-03-25
Clifford Wolf
Add "cutpoint" pass
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2019-03-25
Eddie Hung
Create one $shiftx per bit in width
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2019-03-25
Clifford Wolf
Merge pull request #896 from YosysHQ/transp_fixes
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2019-03-25
Clifford Wolf
Merge pull request #897 from trcwm/libertyfixes
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2019-03-25
Niels Moseley
spaces -> tabs
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2019-03-25
Niels Moseley
EOL is now accepted as ';' replacement on lines that...
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2019-03-24
Niels Moseley
Updated the liberty parser to accept [A:B] ranges ...
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2019-03-24
David Shah
memory_bram: Fix multiclock make_transp
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2019-03-23
Eddie Hung
Add a pmux-to-shiftx optimisation to proc_mux
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2019-03-23
Clifford Wolf
Add "mutate -none -mode", "mutate -mode none"
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2019-03-23
Clifford Wolf
Add "mutate -s <filename>"
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2019-03-23
Clifford Wolf
Merge pull request #893 from YosysHQ/clifford/btormeminit
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2019-03-23
Clifford Wolf
Add support for memory initialization to write_btor
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2019-03-23
Clifford Wolf
Fix BTOR output tags syntax in writye_btor
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2019-03-23
Clifford Wolf
Add RTLIL::Const::ext[su](), fix RTLIL::SigSpec::extend...
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2019-03-22
Clifford Wolf
Merge pull request #889 from YosysHQ/clifford/fix888
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2019-03-22
Clifford Wolf
Merge pull request #890 from YosysHQ/clifford/fix887
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2019-03-22
David Shah
Merge pull request #891 from YosysHQ/xilinx_keep
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2019-03-22
David Shah
xilinx: Add keep attribute where appropriate
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2019-03-22
Clifford Wolf
Trim init attributes when resizing FFs in "wreduce...
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2019-03-21
Clifford Wolf
Fix mem2reg handling of memories with upto data ports...
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2019-03-21
Clifford Wolf
Improve "read_verilog -dump_vlog[12]" handling of upto...
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2019-03-21
Clifford Wolf
Improve read_verilog debug output capabilities
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2019-03-19
Clifford Wolf
Merge pull request #885 from YosysHQ/clifford/fix873
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2019-03-19
Clifford Wolf
Add Xilinx negedge FFs to synth_xilinx dffinit call...
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2019-03-19
Eddie Hung
Merge pull request #808 from eddiehung/read_aiger
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2019-03-19
Eddie Hung
Merge https://github.com/YosysHQ/yosys into read_aiger
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2019-03-19
Eddie Hung
Add author name
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2019-03-19
Clifford Wolf
Merge pull request #884 from zachjs/master
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2019-03-19
Zachary Snow
fix local name resolution in prefix constructs
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2019-03-17
Clifford Wolf
Update issue template
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2019-03-17
Clifford Wolf
Update issue template
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2019-03-16
Clifford Wolf
Merge pull request #877 from FelixVi/master
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2019-03-16
Felix Vietmeyer
Add note about test requirements in README
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2019-03-15
Clifford Wolf
Improve mix of src/wire/wirebit coverage in "mutate...
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2019-03-15
Clifford Wolf
Merge pull request #876 from YosysHQ/clifford/fmcombine
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2019-03-15
Clifford Wolf
Add "fmcombine -fwd -bwd -nop"
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2019-03-15
Clifford Wolf
Add fmcombine pass
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2019-03-14
Clifford Wolf
Merge pull request #875 from YosysHQ/clifford/mutate
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2019-03-14
Clifford Wolf
Disable realmath tests
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2019-03-14
Clifford Wolf
Improvements in "mutate" list-reduce algorithm
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2019-03-14
Clifford Wolf
Add "mutate -cfg", improve pick_cover behavior
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2019-03-14
Clifford Wolf
Add a strictly coverage-driven mutation selection strategy
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2019-03-14
Clifford Wolf
Improve "mutate" wire coverage metric
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2019-03-14
Clifford Wolf
Add more mutation types, improve mutation src cover
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2019-03-14
Clifford Wolf
Fix smtbmc.py handling of zero appended steps
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2019-03-14
Clifford Wolf
Add "mutate" command DB reduce functionality
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2019-03-14
Clifford Wolf
Add hashlib "<container>::element(int n)" methods
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