2021-06-25 |
Luke Kenneth... | identify SVP64 LD bit-reverse pattern as pseudo-assembler |
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2021-06-25 |
Luke Kenneth... | only set conditions in PowerDecoder2 for svp64 mode |
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2021-06-25 |
Luke Kenneth... | update sv_analysis.py to match new CONDITIONs field... |
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2021-06-25 |
Luke Kenneth... | rename svp64 bit-reversed LD instructions to not confli... |
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2021-06-24 |
Luke Kenneth... | whoops SVP64 bit-rev LDs need to use SVD and SVDS immed... |
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2021-06-24 |
Luke Kenneth... | allow default decoder to be created with no col/row... |
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2021-06-24 |
Luke Kenneth... | add in Power Decoder conditions to select SVP64 bit... |
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2021-06-24 |
Luke Kenneth... | add "conditions" for PowerDecoder, basic test |
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2021-06-24 |
Luke Kenneth... | remove svp64 ld/st decoder tree |
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2021-06-24 |
Luke Kenneth... | must pass in conditions into Sub-decoders |
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2021-06-24 |
Luke Kenneth... | search for CSV "Conditions", set to static (disabled... |
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2021-06-24 |
Luke Kenneth... | add major.csv LD operations with SVP64BREV condition |
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2021-06-24 |
Luke Kenneth... | add PowerDecoder condition switches (untested, doesnt... |
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2021-06-24 |
Luke Kenneth... | was going to set 2nd decoder up through MUX but now... |
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2021-06-24 |
Luke Kenneth... | add extra CONDITION column to CSVs |
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2021-06-24 |
Luke Kenneth... | whoops fix rounding error in mapreduce unit test |
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2021-06-24 |
Luke Kenneth... | only add svdecldst in PowerDecoder2 or LDST PowerDecode... |
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2021-06-24 |
Luke Kenneth... | use PowerOp copy of PowerDecodeSubset in get_op |
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2021-06-24 |
Luke Kenneth... | add "user_svp64_ldst_dec" flag to PowerDecodeSubset |
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2021-06-24 |
Luke Kenneth... | use new PowerOp.like function in PowerDecoder, fix... |
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2021-06-24 |
Luke Kenneth... | use get_op on "internal_op" instead of self.dec.op... |
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2021-06-24 |
Luke Kenneth... | do shorter-path detection of SVP64 LD/ST bitreverse... |
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2021-06-24 |
Luke Kenneth... | tidy up PowerOp and rename svp64 ldst decoder creater |
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2021-06-24 |
Luke Kenneth... | add comment about perfcounters |
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2021-06-23 |
Luke Kenneth... | get op always using function PowerDecoder.op_get |
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2021-06-23 |
Luke Kenneth... | add PowerOp.like function to be able to duplicate a... |
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2021-06-23 |
Luke Kenneth... | add SVP64 alternative LDST decoder (unused so far) |
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2021-06-23 |
Luke Kenneth... | only add SVP64 bitreverse mode for LDs at the moment... |
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2021-06-23 |
Luke Kenneth... | add SVP64 LD/ST "bitrev" alternative CSV |
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2021-06-23 |
Luke Kenneth... | add sv bitrev "major" CSV table |
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2021-06-23 |
Luke Kenneth... | add start of bit-reverse mode for LD/ST to SVP64 encode... |
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2021-06-23 |
Luke Kenneth... | looks like spec error on maddhd etc. should be a comma... |
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2021-06-23 |
Luke Kenneth... | add mul-add to list of instructions |
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2021-06-23 |
Luke Kenneth... | add ASCII art example to int predicated SVP64 |
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2021-06-23 |
Luke Kenneth... | add VL and srcstep to ISACaller namespace |
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2021-06-23 |
Luke Kenneth... | add SHL64 helper function |
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2021-06-23 |
Luke Kenneth... | add bitrev to pywriter autogenerator |
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2021-06-23 |
Luke Kenneth... | add bitrev function to be used in LD-ST-bitrev FFT/DCT |
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2021-06-23 |
Luke Kenneth... | better ways to do sign-inversion (without multiply... |
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2021-06-23 |
Luke Kenneth... | add sign-inversion argument to FPMUL/DIV helpers |
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2021-06-23 |
Luke Kenneth... | add comments for SVP64 FP FFT/DCT |
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2021-06-23 |
Luke Kenneth... | add FFT/DCT to titles |
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2021-06-23 |
Luke Kenneth... | add SV FP arithmetic in "Overflow" mode for FFT/DCT +/- |
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2021-06-23 |
Luke Kenneth... | use SHL64 function for shift because "<<" operator... |
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2021-06-23 |
Luke Kenneth... | add in bitreverse function call into svfixedload |
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2021-06-23 |
Luke Kenneth... | add RC and SVD/SVDS-Form to svfixedload |
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2021-06-23 |
Luke Kenneth... | add svfixedload.mdwn at correct place |
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2021-06-23 |
Luke Kenneth... | add SVD-Form and SVDS-Form, variants of fixedload for... |
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2021-06-19 |
Luke Kenneth... | 128 regs added to simulator - works |
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2021-06-19 |
Luke Kenneth... | sigh cannot add comments at end of SV lines in SVP64... |
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2021-06-19 |
Luke Kenneth... | increase number of registers to 128 in pypowersim |
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2021-06-19 |
Luke Kenneth... | set regfile in ISACaller equal to length of initial... |
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2021-06-19 |
Luke Kenneth... | add mapreduce "reverse gear" unit tests |
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2021-06-19 |
Luke Kenneth... | add mapreduce "reverse gear" to PowerDecoder2. gets... |
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2021-06-19 |
Luke Kenneth... | add decode of "reverse gear" in SVP64 reduce mode |
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2021-06-19 |
Luke Kenneth... | add "reverse-gear" mode to mapreduce in SVP64 |
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2021-06-18 |
Luke Kenneth... | add SV Context SPRs (SVCTX0-7) |
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2021-06-18 |
Luke Kenneth... | add SVR-Form and associated fields |
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2021-06-18 |
Luke Kenneth... | add four SVSHAPE SPRs for REMAP |
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2021-06-17 |
Luke Kenneth... | add SV "Context Propagation" Form |
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2021-06-17 |
Luke Kenneth... | add SVP64REMAP Record |
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2021-06-17 |
Luke Kenneth... | shuffle comments |
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2021-06-17 |
Luke Kenneth... | fix MP3 CODEC basic demo by using fmuls and fadds/fsubs... |
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2021-06-16 |
Luke Kenneth... | sorted out order of FPMULADD32 helper, only have roundi... |
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2021-06-16 |
Luke Kenneth... | add extra comments to mp3 svp64 codec assembler |
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2021-06-16 |
Luke Kenneth... | fix fmadds/fmsubs FPMULADD32 helper |
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2021-06-16 |
Luke Kenneth... | more code-comments in mp3 codec svp64 example |
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2021-06-16 |
Luke Kenneth... | although unused read first sum from *dither_state |
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2021-06-16 |
Luke Kenneth... | use addi where sv.addi is inappropriate (scalar values) |
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2021-06-16 |
Luke Kenneth... | reorder arguments to FPMULADD32 to match pseudocode |
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2021-06-16 |
Luke Kenneth... | use fnmsubs instead of fmadds followed by fsubs |
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2021-06-16 |
Luke Kenneth... | fnmadds and fnmsubs were inverted |
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2021-06-16 |
Luke Kenneth... | ad fnmadd and fnmsubs to ISA pseudocode |
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2021-06-16 |
Luke Kenneth... | reverting removal of tmpsum and tmpsum2, not using... |
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2021-06-15 |
Luke Kenneth... | whoops forgot import |
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2021-06-15 |
Luke Kenneth... | whoops still using DOUBLE(SINGLE(x)) rather than DOUBLE... |
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2021-06-15 |
Luke Kenneth... | remove predicate mask r30, no longer needed |
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2021-06-15 |
Luke Kenneth... | no need for tmpsu or tmpsum2, fmadds if replaced with... |
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2021-06-15 |
Luke Kenneth... | use new sv.fmadds SVP64 instruction in MP3 CODEC assembler |
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2021-06-15 |
Luke Kenneth... | fix sv_analysis.py for 3R-1W-CRo case, add fmadds/fmsub... |
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2021-06-15 |
Luke Kenneth... | mark as possible bug, the fneg sum,sum |
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2021-06-15 |
Luke Kenneth... | add fmadds and fmsubs to Power ISA pseudo-code, add... |
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2021-06-15 |
Luke Kenneth... | remove negate of sum for last value in SVP64 MP3 CODEC... |
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2021-06-15 |
Luke Kenneth... | SVP64 mp3 assembler almost correct |
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2021-06-15 |
Luke Kenneth... | add comments into mapreduce example |
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2021-06-15 |
Luke Kenneth... | whoops overlap of fv0-2 with sum/2/tmp, move further up |
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2021-06-14 |
Luke Kenneth... | sigh bug in setvl, temporarily setting to 7 not 8 |
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2021-06-14 |
Luke Kenneth... | nope, win = win2 + 31 |
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2021-06-14 |
Luke Kenneth... | guessing probably supposed to be 128 not 124 |
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2021-06-14 |
Luke Kenneth... | tmpsum2 probably needed to be fp3 |
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2021-06-14 |
Luke Kenneth... | temporary move regs into range 0-31 |
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2021-06-14 |
Luke Kenneth... | recognise setvl instruction during SVP64 translation |
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2021-06-14 |
Luke Kenneth... | whoops forgot format-to-format conversion |
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2021-06-14 |
Luke Kenneth... | series of text macro formats to look for: x.v, x.s (x) |
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2021-06-14 |
Luke Kenneth... | add basic "macro" (.set) support to SVP64Asm |
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2021-06-14 |
Lauri Kasanen | mp3_0 initial sv |
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2021-06-14 |
Lauri Kasanen | Reorder mp3_0_basicsv back to the C loop style |
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2021-06-14 |
Lauri Kasanen | Update mp3_1.gpr missed in b04990f79c |
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2021-06-09 |
Luke Kenneth... | add some more comments in the mapreduce svp64 examples... |
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2021-06-09 |
Luke Kenneth... | add sv.fmuls/mr - mapreduce - FP multiply-single test |
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next |