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yosys.git
2017-08-20 Clifford WolfRename "singleton" pass to "uniquify" commit | commitdiff | tree
2017-08-18 Clifford WolfMore intuitive handling of "cd .." for singleton modules commit | commitdiff | tree
2017-08-18 Clifford WolfAdd "sim -zinit -rstlen" commit | commitdiff | tree
2017-08-18 Clifford WolfMerge branch 'sim' commit | commitdiff | tree
2017-08-18 Clifford WolfAdd "sim" support for memories commit | commitdiff | tree
2017-08-18 Clifford WolfAdd Const methods is_fully_zero(), is_fully_def(),... commit | commitdiff | tree
2017-08-18 Clifford WolfAdd support for assert/assume/cover to "sim" command commit | commitdiff | tree
2017-08-17 Clifford WolfAdd writeback mode to "sim" command commit | commitdiff | tree
2017-08-17 Clifford WolfImprove "sim" command commit | commitdiff | tree
2017-08-16 Clifford WolfMerge pull request #386 from azonenberg/gpak-counters commit | commitdiff | tree
2017-08-16 Clifford WolfAdd "sim" command skeleton commit | commitdiff | tree
2017-08-15 Andrew ZonenbergFixed more issues with GreenPAK counter sim models commit | commitdiff | tree
2017-08-15 Andrew ZonenbergUpdated PGEN model to have level triggered reset (match... commit | commitdiff | tree
2017-08-15 Andrew ZonenbergFixed bug in GP_COUNTx model commit | commitdiff | tree
2017-08-15 Andrew ZonenbergFixed bug where GP_COUNTx_ADV would wrap even when... commit | commitdiff | tree
2017-08-15 Clifford WolfMerge branch 'azonenberg-rmports' commit | commitdiff | tree
2017-08-15 Clifford WolfMostly coding style related fixes in rmports pass commit | commitdiff | tree
2017-08-15 Clifford WolfMerge branch 'rmports' of https://github.com/azonenberg... commit | commitdiff | tree
2017-08-14 Clifford WolfMerge pull request #381 from azonenberg/countfix commit | commitdiff | tree
2017-08-14 Clifford WolfMerge pull request #383 from azonenberg/abcfnames commit | commitdiff | tree
2017-08-14 Clifford WolfMerge pull request #382 from azonenberg/jsoniofix commit | commitdiff | tree
2017-08-14 Clifford WolfMerge pull request #384 from azonenberg/crtechlib commit | commitdiff | tree
2017-08-14 Robert Oucoolrunner2: Add INVERT parameter to some BUFGs commit | commitdiff | tree
2017-08-14 Robert Oucoolrunner2: Add FFs with clock enable to cells_sim.v commit | commitdiff | tree
2017-08-14 Robert Ouabc: Allow +/ filenames in the abc command commit | commitdiff | tree
2017-08-14 Robert Oujson: Parse inout correctly rather than as an output commit | commitdiff | tree
2017-08-14 Andrew Zonenbergrmports: Now remove ports from cell instances if we... commit | commitdiff | tree
2017-08-14 Andrew ZonenbergProcessModule is no longer virtual (why was it in the... commit | commitdiff | tree
2017-08-14 Andrew Zonenbergrmports now works on all modules in the design, not... commit | commitdiff | tree
2017-08-14 Andrew ZonenbergUpdated Makefile to reflect opt_rmports being renamed... commit | commitdiff | tree
2017-08-14 Andrew ZonenbergRenamed opt_rmports pass to rmports commit | commitdiff | tree
2017-08-14 Andrew ZonenbergFixed typo in GP_COUNT8 sim model commit | commitdiff | tree
2017-08-14 Andrew ZonenbergFixed typo in error message commit | commitdiff | tree
2017-08-14 Andrew ZonenbergChanged LEVEL resets for GP_COUNTx to be properly synth... commit | commitdiff | tree
2017-08-14 Andrew ZonenbergChanged LEVEL resets to be edge triggered anyway commit | commitdiff | tree
2017-08-14 Andrew ZonenbergAdded level-triggered reset support to GP_COUNTx simula... commit | commitdiff | tree
2017-08-14 Andrew ZonenbergFixed undeclared "count" in GP_COUNT8_ADV commit | commitdiff | tree
2017-08-14 Andrew ZonenbergFixed undeclared "count" in GP_COUNT14_ADV commit | commitdiff | tree
2017-08-14 Andrew ZonenbergFixed typo in last commit commit | commitdiff | tree
2017-08-14 Andrew ZonenbergFinished initial GP_COUNT8/14/8_ADV/14_ADV sim models... commit | commitdiff | tree
2017-08-14 Andrew ZonenbergFixed typo in COUNT8 model commit | commitdiff | tree
2017-08-14 Andrew ZonenbergMoved GP_POR out of digital cells b/c it has delays commit | commitdiff | tree
2017-08-14 Andrew ZonenbergImproved cells_sim_digital model for GP_COUNT8 commit | commitdiff | tree
2017-08-14 Andrew ZonenbergRefactored GreenPAK4 cells_sim into cells_sim_ams and... commit | commitdiff | tree
2017-08-14 Andrew ZonenbergImproved handling of constant connections in opt_rmports commit | commitdiff | tree
2017-08-14 Andrew ZonenbergFixed handling of cell ports that aren't wires commit | commitdiff | tree
2017-08-14 Andrew Zonenbergopt_rmports: Fixed incorrect handling of multi-bit... commit | commitdiff | tree
2017-08-14 Andrew ZonenbergRemoved commented out debug code commit | commitdiff | tree
2017-08-14 Andrew ZonenbergAdded opt_rmports pass (remove unconnected ports from... commit | commitdiff | tree
2017-08-09 Clifford WolfAdd support for set-reset cell variants to opt_rmdff commit | commitdiff | tree
2017-08-09 Clifford WolfAuto-detect JSON front-end commit | commitdiff | tree
2017-08-06 Clifford WolfAdd handling of constant reset signals to opt_rmdff commit | commitdiff | tree
2017-08-04 Clifford WolfAdd "yosys-smtbmc --smtc-init --smtc-top --noinit" commit | commitdiff | tree
2017-08-04 Clifford WolfAdd "-undefined dynamic_lookup" to OSX "yosys-config... commit | commitdiff | tree
2017-07-29 Clifford WolfFix typo in "abc" pass help message commit | commitdiff | tree
2017-07-28 Clifford WolfAdd merging of "past FFs" to verific importer commit | commitdiff | tree
2017-07-28 Clifford WolfAdd consolidation of init attributes to opt_clean,... commit | commitdiff | tree
2017-07-28 Clifford WolfAdd minimal support for PSL in VHDL via Verific commit | commitdiff | tree
2017-07-28 Clifford WolfAdd simple VHDL+PSL example commit | commitdiff | tree
2017-07-28 Clifford WolfImprove Verific HDL language options commit | commitdiff | tree
2017-07-28 Clifford WolfFix handling of non-user-declared Verific netbus commit | commitdiff | tree
2017-07-27 Clifford WolfImprove Verific SVA importer commit | commitdiff | tree
2017-07-27 Clifford WolfAdd counter.sv SVA test commit | commitdiff | tree
2017-07-27 Clifford WolfAdd log_warning_noprefix() API, Use for Verific warning... commit | commitdiff | tree
2017-07-27 Clifford WolfAdd "verific -import -n" and "verific -import -nosva" commit | commitdiff | tree
2017-07-27 Clifford WolfImprove SVA tests, add Makefile and scripts commit | commitdiff | tree
2017-07-27 Clifford WolfImprove Verific SVA import: negedge and $past commit | commitdiff | tree
2017-07-27 Clifford WolfImprove Verific SVA importer commit | commitdiff | tree
2017-07-26 Clifford WolfAdd "opt_expr -fine" feature to remove neutral bits... commit | commitdiff | tree
2017-07-26 Clifford WolfImprove Verific bindings (mostly related to SVA) commit | commitdiff | tree
2017-07-25 Clifford WolfImprove "help verific" message commit | commitdiff | tree
2017-07-25 Clifford WolfAdd "verific -extnets" commit | commitdiff | tree
2017-07-25 Clifford WolfAdd "using std::get" to yosys.h commit | commitdiff | tree
2017-07-25 Clifford WolfImprove "verific -all" handling commit | commitdiff | tree
2017-07-24 Clifford WolfAdd "verific -import -d <dump_file" commit | commitdiff | tree
2017-07-24 Clifford WolfAdd "verific -import -flatten" and "verific -import -v" commit | commitdiff | tree
2017-07-22 Clifford WolfAdd more SVA test cases for future Verific work commit | commitdiff | tree
2017-07-22 Clifford WolfAdd "verific -import -k" commit | commitdiff | tree
2017-07-22 Clifford WolfAdd error for cell output ports that are connected... commit | commitdiff | tree
2017-07-22 Clifford WolfAdd some simple SVA test cases for future Verific work commit | commitdiff | tree
2017-07-22 Clifford WolfImprove docs for verific bindings, add simply sby example commit | commitdiff | tree
2017-07-21 Clifford WolfFix handling of empty cell port assignments (i.e. ignor... commit | commitdiff | tree
2017-07-21 Clifford WolfFix "read_blif -wideports" handling of cells with wide... commit | commitdiff | tree
2017-07-21 Clifford WolfAdd a paragraph about pre-defined macros to read_verilo... commit | commitdiff | tree
2017-07-21 Clifford WolfAdd verilator support to testbenches generated by yosys... commit | commitdiff | tree
2017-07-18 Clifford WolfChange intptr_t to uintptr_t in hashlib.h commit | commitdiff | tree
2017-07-18 Clifford WolfMerge pull request #363 from rqou/master commit | commitdiff | tree
2017-07-17 Robert Oumakefile: Add the option to use libtermcap commit | commitdiff | tree
2017-07-17 Robert OuFix build warnings for win64 commit | commitdiff | tree
2017-07-14 Clifford WolfAdd $alu to list of supported cells for "stat -width" commit | commitdiff | tree
2017-07-12 Clifford WolfGenerate FSM-style testbenches in smtbmc commit | commitdiff | tree
2017-07-11 Clifford WolfFix the fixed handling of x-bits in EDIF back-end commit | commitdiff | tree
2017-07-11 Clifford WolfFix handling of x-bits in EDIF back-end commit | commitdiff | tree
2017-07-10 Clifford WolfAdd attributes and parameter support to JSON front-end commit | commitdiff | tree
2017-07-10 Clifford WolfAdd techlibs/xilinx/lut2lut.v commit | commitdiff | tree
2017-07-08 Clifford WolfAdd JSON front-end commit | commitdiff | tree
2017-07-07 Clifford WolfChange s/asserts/assertions/ in yosys-smtbmc log messages commit | commitdiff | tree
2017-07-07 Clifford WolfAdd "yosys-smtbmc --presat" commit | commitdiff | tree
2017-07-05 Clifford WolfFix generation of multiple outputs for same AIG node... commit | commitdiff | tree
2017-07-05 Clifford WolfAdd write_table command commit | commitdiff | tree
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