| 2014-08-12 |
Clifford Wolf | Added multi-dim memory test (requires iverilog git... |
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| 2014-08-11 |
Clifford Wolf | Another build fix by americanrouter (via reddit) |
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| 2014-08-10 |
Clifford Wolf | Fixed FSM mapping for multiple reset-like signals |
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| 2014-08-09 |
Clifford Wolf | Fixed "share" for complex scenarios with never-active... |
commit | commitdiff | tree |
| 2014-08-09 |
Clifford Wolf | Do not share any $reduce_* cells (its complicated and... |
commit | commitdiff | tree |
| 2014-08-09 |
Clifford Wolf | Some improvements in fsm_opt and fsm_map for FSM with... |
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| 2014-08-08 |
Clifford Wolf | Improved FSM tests |
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| 2014-08-08 |
Clifford Wolf | Another fsm_extract bugfix |
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| 2014-08-08 |
Clifford Wolf | Fixed "fsm -export" |
commit | commitdiff | tree |
| 2014-08-08 |
Clifford Wolf | Fixed sharing of reduce operator |
commit | commitdiff | tree |
| 2014-08-08 |
Clifford Wolf | Fixed fsm_extract for wreduced muxes |
commit | commitdiff | tree |
| 2014-08-08 |
Clifford Wolf | Added FSM test bench |
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| 2014-08-08 |
Clifford Wolf | Added "sat -prove-skip" |
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| 2014-08-07 |
Clifford Wolf | Fixed build with gcc-4.6 |
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| 2014-08-07 |
Clifford Wolf | Use "-keepdc" in "miter -equiv -flatten" |
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| 2014-08-07 |
Clifford Wolf | Also allow "module foobar(input foo, output bar, .... |
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| 2014-08-07 |
Clifford Wolf | Added adff2dff.v (for techmap -share_map) |
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| 2014-08-06 |
Clifford Wolf | Added AST_MULTIRANGE (arrays with more than 1 dimension) |
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| 2014-08-06 |
Clifford Wolf | Various improvements in memory_dff pass |
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| 2014-08-05 |
Clifford Wolf | Various fixes and improvements in wreduce pass |
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| 2014-08-05 |
Clifford Wolf | Removed old "constmap" from wreduce code |
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| 2014-08-05 |
Clifford Wolf | Added support for truncating of wires to wreduce pass |
commit | commitdiff | tree |
| 2014-08-05 |
Clifford Wolf | Cleanups and improvements in wreduce pass |
commit | commitdiff | tree |
| 2014-08-05 |
Clifford Wolf | Added mux support to wreduce command |
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| 2014-08-05 |
Clifford Wolf | Improved scope resolution of local regs in Verilog... |
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| 2014-08-05 |
Clifford Wolf | Fixed AST handling of variables declared inside a funct... |
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| 2014-08-04 |
Clifford Wolf | Added "show -signed" |
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| 2014-08-04 |
Clifford Wolf | Added support for non-standard "module mod_name(..... |
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| 2014-08-04 |
Clifford Wolf | Added RTLIL::IdString::in(...) |
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| 2014-08-03 |
Clifford Wolf | Fixed "share" for memory read ports |
commit | commitdiff | tree |
| 2014-08-03 |
Clifford Wolf | Added "wreduce" to some of the standard test benches |
commit | commitdiff | tree |
| 2014-08-03 |
Clifford Wolf | Progress in "wreduce" pass |
commit | commitdiff | tree |
| 2014-08-03 |
Clifford Wolf | Added "wreduce" command (work in progress) |
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| 2014-08-03 |
Clifford Wolf | Added query() API to ModIndex |
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| 2014-08-03 |
Clifford Wolf | Added ID() macro for static IdStrings |
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| 2014-08-03 |
Clifford Wolf | Implemented recursive techmap |
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| 2014-08-03 |
Clifford Wolf | Fixes in show command (related to new IdString) |
commit | commitdiff | tree |
| 2014-08-02 |
Clifford Wolf | Implemented simplemap support for "techmap -extern" |
commit | commitdiff | tree |
| 2014-08-02 |
Clifford Wolf | Fixed a va_list corruption in logv_error() |
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| 2014-08-02 |
Clifford Wolf | Be more conservative with printing decimal numbers... |
commit | commitdiff | tree |
| 2014-08-02 |
Clifford Wolf | Improved verilog output for ordinary $mux cells |
commit | commitdiff | tree |
| 2014-08-02 |
Clifford Wolf | Bugfix in "techmap -extern" |
commit | commitdiff | tree |
| 2014-08-02 |
Clifford Wolf | Removed at() method from RTLIL::IdString |
commit | commitdiff | tree |
| 2014-08-02 |
Clifford Wolf | No implicit conversion from IdString to anything else |
commit | commitdiff | tree |
| 2014-08-02 |
Clifford Wolf | More bugfixes related to new RTLIL::IdString |
commit | commitdiff | tree |
| 2014-08-02 |
Clifford Wolf | Limit size of log_signal buffer to 100 elements |
commit | commitdiff | tree |
| 2014-08-02 |
Clifford Wolf | Improvements in new RTLIL::IdString implementation |
commit | commitdiff | tree |
| 2014-08-02 |
Clifford Wolf | Fixed a performance bug in opt_reduce |
commit | commitdiff | tree |
| 2014-08-02 |
Clifford Wolf | Implemented new reference counting RTLIL::IdString |
commit | commitdiff | tree |
| 2014-08-02 |
Clifford Wolf | Fixed memory corruption related to id2cstr() |
commit | commitdiff | tree |
| 2014-08-02 |
Clifford Wolf | More cleanups related to RTLIL::IdString usage |
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| 2014-08-01 |
Clifford Wolf | Preparations for RTLIL::IdString redesign: cleanup... |
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| 2014-08-01 |
Clifford Wolf | Added logfile hash to statistics footer |
commit | commitdiff | tree |
| 2014-08-01 |
Clifford Wolf | Replaced sha1 implementation |
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| 2014-08-01 |
Clifford Wolf | Added per-pass cpu usage statistics |
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| 2014-08-01 |
Clifford Wolf | Added ModIndex helper class, some changes to RTLIL... |
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| 2014-08-01 |
Clifford Wolf | Packed SigBit::data and SigBit::offset in a union |
commit | commitdiff | tree |
| 2014-08-01 |
Clifford Wolf | Consolidated hana test benches into fewer files |
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| 2014-08-01 |
Clifford Wolf | Added "test_autotb -n <num_iter>" option |
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| 2014-07-31 |
Clifford Wolf | Renamed modwalker.h to modtools.h |
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| 2014-07-31 |
Clifford Wolf | Various cleanups in Makefile, Renamed default configura... |
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| 2014-07-31 |
Clifford Wolf | Added compiler + compiler version + compiler flags... |
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| 2014-07-31 |
Clifford Wolf | Fixed build of verific bindings |
commit | commitdiff | tree |
| 2014-07-31 |
Clifford Wolf | Renamed port access function on RTLIL::Cell, added... |
commit | commitdiff | tree |
| 2014-07-31 |
Clifford Wolf | Added "trace" command |
commit | commitdiff | tree |
| 2014-07-31 |
Clifford Wolf | Added RTLIL::Monitor |
commit | commitdiff | tree |
| 2014-07-31 |
Clifford Wolf | Added module->design and cell->module, wire->module... |
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| 2014-07-31 |
Clifford Wolf | Moved some stuff to kernel/yosys.{h,cc}, using Yosys... |
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| 2014-07-31 |
Clifford Wolf | Renamed "stdcells.v" to "techmap.v" |
commit | commitdiff | tree |
| 2014-07-31 |
Clifford Wolf | Added "techmap -assert" |
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| 2014-07-31 |
Clifford Wolf | Reorganized stdcells.v (no actual code change, just... |
commit | commitdiff | tree |
| 2014-07-30 |
Clifford Wolf | Added "yosys -A" |
commit | commitdiff | tree |
| 2014-07-30 |
Clifford Wolf | Added "yosys -Q" |
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| 2014-07-30 |
Clifford Wolf | Added techmap CONSTMAP feature |
commit | commitdiff | tree |
| 2014-07-30 |
Clifford Wolf | Fixed counting verilog line numbers for "// synopsys... |
commit | commitdiff | tree |
| 2014-07-30 |
Clifford Wolf | Added write_file command |
commit | commitdiff | tree |
| 2014-07-30 |
Clifford Wolf | Added "make -j{N}" support to "make test" |
commit | commitdiff | tree |
| 2014-07-30 |
Clifford Wolf | Improvements in test_cell |
commit | commitdiff | tree |
| 2014-07-30 |
Clifford Wolf | New techmap default rules for $shr $sshr $shl $sshl |
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| 2014-07-30 |
Clifford Wolf | Using native ezSAT shift ops in satgen, fixed $shift... |
commit | commitdiff | tree |
| 2014-07-30 |
Clifford Wolf | Added native support for shift operations to ezSAT |
commit | commitdiff | tree |
| 2014-07-30 |
Clifford Wolf | Added "log_dump_val_worker(char *v)" |
commit | commitdiff | tree |
| 2014-07-30 |
Clifford Wolf | Added CodingStyle document |
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| 2014-07-30 |
Clifford Wolf | Added "kernel/yosys.h" and "kernel/yosys.cc" |
commit | commitdiff | tree |
| 2014-07-29 |
Clifford Wolf | Added "test_cell" command |
commit | commitdiff | tree |
| 2014-07-29 |
Clifford Wolf | Renamed "write_autotest" to "test_autotb" and moved... |
commit | commitdiff | tree |
| 2014-07-29 |
Clifford Wolf | Fixed Verilog pre-processor for files with no trailing... |
commit | commitdiff | tree |
| 2014-07-29 |
Clifford Wolf | Bugfix in simlib.v for iverilog |
commit | commitdiff | tree |
| 2014-07-29 |
Clifford Wolf | Allow "hierarchy -generate" for $__ cells |
commit | commitdiff | tree |
| 2014-07-29 |
Clifford Wolf | Added "techmap -map %{design-name}" |
commit | commitdiff | tree |
| 2014-07-29 |
Clifford Wolf | Added $shift and $shiftx cell types (needed for correct... |
commit | commitdiff | tree |
| 2014-07-28 |
Clifford Wolf | Removed left over debug code |
commit | commitdiff | tree |
| 2014-07-28 |
Clifford Wolf | Fixed part selects of parameters |
commit | commitdiff | tree |
| 2014-07-28 |
Clifford Wolf | Set results of out-of-bounds static bit/part select... |
commit | commitdiff | tree |
| 2014-07-28 |
Clifford Wolf | Fixed RTLIL code generator for part select of parameter |
commit | commitdiff | tree |
| 2014-07-28 |
Clifford Wolf | Fixed width detection for part selects |
commit | commitdiff | tree |
| 2014-07-28 |
Clifford Wolf | Added support for "upto" wires to Verilog front- and... |
commit | commitdiff | tree |
| 2014-07-28 |
Clifford Wolf | Added wire->upto flag for signals such as "wire [0... |
commit | commitdiff | tree |
| 2014-07-28 |
Clifford Wolf | Using log_assert() instead of assert() |
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| 2014-07-28 |
Clifford Wolf | Added std::initializer_list<> constructor to SigSpec |
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