riscv-isa-sim.git
2016-05-23 Tim NewsomeProperly save/restore dpc, mcause, mbadaddr.
2016-05-23 Tim NewsomeExceptions in Debug Mode, stay in Debug Mode.
2016-05-23 Tim NewsomeRemove debug printfs.
2016-05-23 Tim NewsomeHave Debug memory kind of working again.
2016-05-23 Tim NewsomeRead FP registers, and general CSRs*
2016-05-23 Tim NewsomeContinue works well enough for DebugTest.test_exit
2016-05-23 Tim NewsomeFix race using fence.
2016-05-23 Tim NewsomeRefactor how we track in-progress operations.
2016-05-23 Tim Newsomegdb can attach and read the PC:
2016-05-23 Tim Newsomeprocessor_t unfriends gdbserver_t.
2016-05-23 Tim NewsomeCorrectly read PC on halt.
2016-05-23 Tim NewsomeFix store to clear debug interrupt.
2016-05-23 Tim NewsomeAdd debug_module bus device.
2016-05-23 Tim NewsomeROM -> RAM -> ROM, waiting for debug int.
2016-05-23 Tim NewsomeMake sure to translate Debug RAM addresses also.
2016-05-23 Tim NewsomeJump to the correct (temporary) Debug RAM address.
2016-05-23 Tim NewsomeClean up how Debug ROM is included.
2016-05-23 Tim NewsomeCan jump to and execute Debug ROM.
2016-05-23 Tim NewsomeCheck in compiled debug ROM.
2016-05-23 Tim NewsomeWhen gdb connects, jump to Debug ROM and segfault.
2016-05-23 Tim NewsomeAdd debug rom code.
2016-05-23 Tim NewsomeGutting direct-access gdb.
2016-05-23 Tim NewsomeAdd writing to DCSR, DPC, DSCRATCH.
2016-05-23 Tim NewsomeActually run the ebreak test.
2016-05-23 Tim NewsomeOnly halt on ebreak if a debugger is attached.
2016-05-23 Tim NewsomeTest ebreak without gdb.
2016-05-23 Tim NewsomeDocument attaching with gdb.
2016-05-23 Tim NewsomeAdd --gdb-port
2016-05-23 Tim NewsomeDo a better job checking CSR functionality.
2016-05-23 Tim NewsomeRename gdbserver-smoke.py to gdbserver.py.
2016-05-23 Tim NewsomeTest 'info registers all' as well as 'info all-registers'
2016-05-23 Tim NewsomeMinor cleanup.
2016-05-23 Tim NewsomeUpdate regnum handling to match gdb CSR changes.
2016-05-23 Tim NewsomeForgot to add this source.
2016-05-23 Tim NewsomeTreat warnings as errors.
2016-05-23 Tim NewsomeImplement register writes.
2016-05-23 Tim NewsomeProperly clean up spike.
2016-05-23 Tim NewsomeImplement reading of CSRs.
2016-05-23 Tim NewsomeAdd some tests that pass and test something.
2016-05-23 Tim NewsomeFlush icache when using swbps and report to gdb.
2016-05-23 Tim NewsomeAdd very basic 'make check'.
2016-05-23 Tim NewsomeMake 'make check' not hang forever.
2016-05-23 Tim NewsomeSoftware breakpoints seem to work.
2016-05-23 Tim NewsomeRewrite GPL'd code from OpenOCD.
2016-05-23 Tim NewsomeLooks like single step works.
2016-05-23 Tim NewsomeAdd -H to start halted.
2016-05-23 Tim NewsomeImplement binary memory write.
2016-05-23 Tim NewsomeNow you can halt/continue from gdb.
2016-05-23 Tim NewsomeRegister read looks sane now.
2016-05-23 Tim Newsomegdb can now read spike memory.
2016-05-23 Tim NewsomeHack to the point where gdb reads a register.
2016-05-23 Tim NewsomeListen on a socket for gdb to connect to.
2016-05-22 Andrew WatermanAllow delegation of device interrupts
2016-05-21 Garret Kellyhtif: catch proper store exception (#44)
2016-05-21 Andy WrightSome bugfixes for CSR reading and setting FS for fflags...
2016-05-19 Tim NewsomeMerge pull request #42 from csail-csg/master
2016-05-19 acw1251Removed devicetree.h from riscv.mk.in since it no longe...
2016-05-18 acw1251Added missing header files to riscv.mk.in
2016-05-02 Andrew WatermanAdd back IPI support
2016-05-02 Andrew WatermanRemove MIPI; mip.MSIP bit is read-only
2016-05-02 Andrew WatermanRemove tohost/fromhost registers
2016-05-01 Andrew WatermanInitialize mtvec to DEFAULT_MTVEC
2016-05-01 Andrew WatermanRemove SCRs; add padding after config string
2016-04-29 Andrew WatermanMove much closer to new platform-M memory map
2016-04-28 Andrew WatermanAdd --dump-config-string flag
2016-04-28 Andrew WatermanRemove MTIME[CMP]; add RTC device
2016-04-20 Andrew WatermanSplit ERET into URET, SRET, HRET, MRET
2016-04-06 Andrew WatermanRemove non-standard uarch CSRs
2016-04-03 Andrew WatermanAllow configuration of default ISA with --with-isa
2016-03-17 Andrew WatermanUpdate definition of base field in misa register
2016-03-04 Andrew WatermanFix up interrupt delegation
2016-03-02 Andrew WatermanAdd counter-enable registers
2016-03-02 Andrew WatermanUse RV config string rather than FDT
2016-03-02 Andrew WatermanWIP on priv spec v1.9
2016-03-02 Andrew WatermanNew definitions of misa/marchid/mvendorid
2016-03-02 Andrew Watermanimplement PUM functionality
2016-03-02 Andrew Watermansptbr now a holds a PPN, not an address
2016-03-02 Andrew WatermanReturn to interactive mode after a trap
2016-03-02 Andrew WatermanUse simpler MTVEC scheme
2016-03-02 Andrew WatermanFix ERET bug
2016-03-02 Andrew WatermanZero-extend all CSR writes
2016-03-02 Andrew WatermanFix ERET serialization strategy
2016-03-02 Andrew WatermanAdd autoconf check for little-endianness
2016-03-02 Andrew WatermanSet default RV32 RAM size to 4 GiB - 256 MiB
2016-03-02 Andrew WatermanSerialize simulator on ERET
2016-03-02 Andrew WatermanWIP on priv spec v1.9
2016-03-02 Andrew WatermanCompile debug symbols
2016-03-02 Andrew WatermanMark SoftFloat routines static inline
2016-03-02 Andrew WatermanUpgrade to latest SoftFloat
2016-02-04 Andrew WatermanActually refill ITLB on ITLB miss
2016-01-30 Andrew WatermanFix NaN propagation for fcvt
2016-01-24 Andrew WatermanRemove hwacha support
2016-01-13 Andrew WatermanUse new NaN discipline
2016-01-13 Andrew Watermandon't ignore data value when writing MIPI
2016-01-05 Andrew Watermanfix help message
2015-12-17 Scott Beameranother osx clang compatability fix
2015-11-20 Andrew WatermanC.ADDIW is reserved for rd=0
2015-11-13 Andrew WatermanGenerate device tree for target machine
2015-11-13 Andrew WatermanAccess FP regs through a macro
2015-11-05 Andrew WatermanMerge pull request #34 from zizztux/incorrect_int_reg_count
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