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gem5.git
2015-03-27
Stephan Diestelhorst
mem: Support any number of master-IDs in stride prefetcher
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2015-03-27
Andreas Hansson
mem: Allocate cache writebacks before new MSHRs
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2015-03-27
Andreas Hansson
mem: Cleanup flow for uncacheable accesses
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2015-03-27
Andreas Hansson
mem: Ignore uncacheable MSHRs when finding matches
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2015-03-27
Andreas Hansson
mem: Remove redundant allocateUncachedReadBuffer in...
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2015-03-27
Andreas Hansson
mem: Modernise MSHR iterators to C++11
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2015-03-27
Andreas Hansson
tests: Update stats for cache block alignment
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2015-03-27
Andreas Hansson
mem: Align all MSHR entries to block boundaries
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2015-03-27
Ali Jafri
mem: Rename PREFETCH_SNOOP_SQUASH flag to BLOCK_CACHED
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2015-03-26
Curtis Dunham
sim: Update limit_event reuse to final version
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2015-03-26
Andreas Hansson
cpu: Fix InstPBTrace inheritance
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2015-03-23
Steve Reinhardt
mem: rename Locked/LOCKED to LockedRMW/LOCKED_RMW
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2015-03-23
Steve Reinhardt
config: expand '~' and '~user' in paths
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2015-03-23
Steve Reinhardt
misc: quote args in echoed command line
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2015-03-23
Curtis Dunham
config: Add ability to exit simulation after initialization
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2015-03-23
Curtis Dunham
sim: Reuse the same limit_event in simulate()
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2015-03-23
Andreas Hansson
mem: Tidy up Request
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2015-03-23
Andreas Hansson
tests: Final reclassification of quick regressions
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2015-03-19
Steve Reinhardt
stats: update Minor stats due to PF bug fix
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2015-03-19
Andreas Hansson
tests: Recategorise regressions based on run time
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2015-03-19
Andreas Sandberg
test, arm: Add scripts to test checkpoints
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2015-03-19
Andreas Hansson
config: Add soak test for memtest.py
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2015-03-19
Matt Evans
arm: Add a GICv2m device
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2015-03-19
Matt Evans
arm: Remove the 'magic MSI register' in the GIC (PL390)
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2015-03-19
Chris Emmons
config: Specify OS type and release on command line
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2015-03-19
Wendy Elsasser
cpu: Fix TrafficGen message format
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2015-03-19
Andreas Hansson
mem: Use emplace front/back for deferred packets
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2015-03-19
Geoffrey Blake
mem: Enable CommMonitor to output traces in atomic...
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2015-03-19
Andreas Hansson
config: Fix DRAM rank option in sweep script
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2015-03-19
Andreas Hansson
tests: Bump timeout to 5 hours
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2015-02-11
Steve Reinhardt
mem: remove redundant test in in Cache::recvTimingResp()
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2015-02-11
Steve Reinhardt
mem: add local var in Cache::recvTimingResp()
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2015-02-11
Steve Reinhardt
mem: restructure Packet cmd initialization a bit more
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2015-03-14
Steve Reinhardt
mem: clean up write buffer check in Cache::handleSnoop()
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2015-03-09
Nilay Vaish
tests: remove not maintained 20.eio-short detailed...
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2015-03-09
Nilay Vaish
stats: changes to due to recent set of patches
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2015-03-09
Rizwana Begum
config: Fix for 'android' lookup in disk name
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2015-03-09
Nilay Vaish
cpu: o3: another assert instead of check
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2015-03-09
Nilay Vaish
cpu: o3: Remove unused code in iew, add assert instead.
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2015-03-09
Nilay Vaish
cpu: o3: commit: mark pipeline delay variable as consts
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2015-03-09
Nilay Vaish
cpu: o3: remove unused stat variables.
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2015-03-09
Nilay Vaish
cpu: o3: combine if with same condition
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2015-03-09
Nilay Vaish
cpu: o3: remove member variable squashCounter
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2015-03-09
Nilay Vaish
cpu: o3: remove unused function annotateMemoryUnits()
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2015-03-07
Steve Reinhardt
stats: update eio stats
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2015-03-02
Andreas Hansson
stats: Update stats to reflect cache and interconnect...
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2015-03-02
Andreas Hansson
mem: Unify all cache DPRINTF address formatting
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2015-03-02
Andreas Hansson
mem: Fix cache MSHR conflict determination
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2015-03-02
Andreas Hansson
mem: Add byte mask to Packet::checkFunctional
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2015-03-02
Stephan Diestelhorst
mem: Add option to force in-order insertion in PacketQueue
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2015-03-02
Marco Balboni
mem: Downstream components consumes new crossbar delays
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2015-03-02
Andreas Hansson
mem: Move crossbar default latencies to subclasses
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2015-03-02
Marco Balboni
mem: Add crossbar latencies
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2015-03-02
Andreas Sandberg
dev, arm: Clean up PL011 and rewrite interrupt handling
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2015-03-02
Andreas Hansson
arm: Share a port for the two table walker objects
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2015-03-02
Giacomo Gabrielli
arm: Remove unnecessary dependencies between AArch64...
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2015-03-02
Rekai
cpu: o3 register renaming request handling improved
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2015-03-02
Andreas Hansson
mem: Tidy up the cache debug messages
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2015-03-02
Andreas Hansson
mem: Split port retry for all different packet classes
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2015-03-02
Ali Jafri
mem: Fix prefetchSquash + memInhibitAsserted bug
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2015-03-02
Stephan Diestelhorst
cpu: Add a PC-value to the traffic generator requests
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2015-03-02
Andreas Hansson
tests: Run regression timeout as foreground
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2015-03-02
Andreas Sandberg
arm: Don't truncate 16-bit ASIDs to 8 bits
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2015-03-02
Andreas Sandberg
arm: Correctly access the stack pointer in GDB
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2015-03-02
Andreas Sandberg
arm: Fix broken page table permissions checks in remote GDB
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2015-02-26
Jason Power
Ruby: Update backing store option to propagate through...
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2015-02-16
Andreas Hansson
config: Add memcheck stress test
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2015-02-16
Andreas Hansson
cpu: TrafficGen sinks snoops without complaining
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2015-02-16
Stephan Diestelhorst
mem: Fix initial value problem with MemChecker
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2015-02-16
Andreas Hansson
dev: Fix undefined behaviuor in i8254xGBe
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2015-02-16
Andreas Sandberg
arm: Wire up the GIC with the platform in the base...
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2015-02-16
Andreas Hansson
mem: mmap the backing store with MAP_NORESERVE
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2015-02-16
Andreas Hansson
mem: Use the range cache for lookup as well as access
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2015-02-16
Andreas Hansson
arch: Make readMiscRegNoEffect const throughout
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2015-01-16
Curtis Dunham
config: add --root-device machine parameter
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2015-02-16
Andreas Sandberg
arm: Merge ISA files with pseudo instructions
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2015-02-16
Ali Saidi
cpu: add support for outputing a protobuf formatted...
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2015-02-11
Marco Balboni
mem: Clarification of packet crossbar timings
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2015-02-11
Marco Balboni
mem: Clarify usage of latency in the cache
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2015-02-11
Andreas Sandberg
style: Fix broken m5format command
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2015-02-11
Andreas Sandberg
style: Fix incorrect style checker option name
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2015-02-11
Andreas Hansson
config: Revamp memtest to allow testers on any level
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2015-02-11
Andreas Hansson
stats: Bump the MemTest regression stats
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2015-02-11
Andreas Hansson
cpu: Tidy up the MemTest and make false sharing more...
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2015-02-11
Andreas Sandberg
sim: Move the BaseTLB to src/arch/generic/
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2015-02-11
Andreas Sandberg
base: Add compiler macros to add deprecation warnings
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2015-02-11
Andreas Hansson
base: Do not dereference NULL in CompoundFlag creation
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2015-02-11
Andreas Sandberg
dev: Remove unused system pointer in the Platform base...
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2015-02-07
Alexandru Dutu
cpu: Idle CPU status logic revised
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2015-02-06
Steve Reinhardt
config: rename 'file' var
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2015-02-06
Steve Reinhardt
config: make M5_PATH a real search path
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2015-02-03
Andreas Hansson
mem: Clarify express snoop behaviour
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2015-02-03
Andreas Hansson
mem: Clarify cache behaviour for pending dirty responses
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2015-02-03
Curtis Dunham
base: add an accessor and operators ==,!= to address...
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2015-02-03
Andreas Hansson
config: Add XOR hashing to the DRAM channel interleaving
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2015-02-03
Andreas Hansson
base: Add XOR-based hashed address interleaving
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2015-02-03
Andreas Hansson
config: Adjust DRAM channel interleaving defaults
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2015-02-03
Andreas Sandberg
style: Update the style checker to handle new include...
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2015-02-03
Andreas Sandberg
sim: Remove test for non-NULL this in Event
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2015-02-03
Andreas Sandberg
dev: Correctly clear interrupts in VirtIO PCI
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