litex.git
2012-06-20 Sebastien Bourdeauducqactorlib/sim/SimActor: remove dead time between transac...
2012-06-20 Sebastien Bourdeauducqactorlib/structuring/Pack: drive busy signal
2012-06-20 Sebastien Bourdeauducqflow: perftools
2012-06-20 Sebastien Bourdeauducqexamples/dataflow/structuring: test Cast
2012-06-20 Sebastien Bourdeauducqexamples/dataflow: structuring test
2012-06-20 Sebastien Bourdeauducqactorlib: structuring (untested)
2012-06-17 Sebastien Bourdeauducqactorlib/control: simplify + fix
2012-06-17 Sebastien Bourdeauducqremove spurious module
2012-06-17 Sebastien Bourdeauducqflow/network: fix handling of edges with subrecords...
2012-06-17 Sebastien Bourdeauducqactorlib/control: use numbers of bits instead of maxima
2012-06-17 Sebastien Bourdeauducqflow/plumbing: Combinator/Splitter should not inherit...
2012-06-16 Sebastien Bourdeauducqexamples/flow: Fibonacci demo
2012-06-16 Sebastien Bourdeauducqflow/network: handle default endpoints correctly in...
2012-06-16 Sebastien Bourdeauducqflow/network: require ActorNode be passed to add_connection
2012-06-16 Sebastien Bourdeauducqflow/network: fix ActorNode default params
2012-06-16 Sebastien Bourdeauducqflow/actor: fix busy signal generation for pipelined...
2012-06-16 Sebastien Bourdeauducqflow/actor: add single_sink/single_source retrieval...
2012-06-16 Sebastien Bourdeauducqexamples/flow/arithmetic: cleanup
2012-06-16 Sebastien Bourdeauducqflow: insert splitters
2012-06-16 Sebastien Bourdeauducqexamples/flow/arithmetic: simulate
2012-06-16 Sebastien Bourdeauducqflow: insert combinators and infer plumbing layout
2012-06-15 Sebastien BourdeauducqAbstract actor graphs
2012-06-12 Sebastien Bourdeauducqactorlib: ASMI sequential reader
2012-06-12 Sebastien Bourdeauducqexamples/dataflow/dma: refactor
2012-06-12 Sebastien Bourdeauducqfix SimActor get_fragment
2012-06-12 Sebastien BourdeauducqReorganize examples folder
2012-06-12 Sebastien BourdeauducqPureSimulable
2012-06-12 Sebastien BourdeauducqASMI simulation models
2012-06-10 Sebastien Bourdeauducqwishbone: base TargetModel class
2012-06-10 Sebastien Bourdeauducqbus/wishbone: target model
2012-06-10 Sebastien Bourdeauducqbus/wishbone/Tap: remove ack feature
2012-06-08 Sebastien Bourdeauducqexamples/dataflow: only import nx when needed
2012-06-08 Sebastien Bourdeauducqflow/network: refactor graph
2012-06-08 Sebastien Bourdeauducqflow/ala: fix typo
2012-06-08 Sebastien Bourdeauducqactorlib: WB writer simulation OK
2012-06-08 Sebastien Bourdeauducqactorlib: WB reader simulation OK
2012-06-08 Sebastien BourdeauducqUse super() instead of calling parent constructors...
2012-06-08 Sebastien Bourdeauducqactorlib/sim: use set instead of list to represent...
2012-06-08 Sebastien Bourdeauducqactorlib: generator-based generic simulation actor
2012-06-08 Sebastien Bourdeauducqsim: multiread/multiwrite
2012-06-08 Sebastien Bourdeauducqcorelogic/record: better repr
2012-06-08 Sebastien Bourdeauducqexamples/fir: print Verilog source
2012-06-07 Sebastien Bourdeauducqexamples/fir: plot input and output signals
2012-06-07 Sebastien Bourdeauducqflow: generic parameter passing to Actor from sequentia...
2012-06-07 Sebastien Bourdeauducqflow: fix actor repr
2012-06-07 Sebastien Bourdeauducqflow: refactor scheduling models
2012-05-21 Sebastien Bourdeauducqbank/description: pad unaligned multi-word registers...
2012-05-21 Sebastien BourdeauducqAdd LICENSE file
2012-05-15 Sebastien Bourdeauducqbus/wishbone2asmi: fix cache tag size
2012-05-15 Sebastien Bourdeauducqasmi: dat_wm high to disable data write
2012-04-30 Sebastien Bourdeauducqbus/asmibus/hub: hack to prevent comb loops
2012-04-30 Sebastien Bourdeauducqfhdl/verilog: add option to display which comb blocks...
2012-04-30 Sebastien Bourdeauducqsim: pass extra keyword arguments to Verilog converter
2012-04-08 Sebastien Bourdeauducqfhdl: support len() on signals
2012-04-06 Sebastien Bourdeauducqbank/csrgen: allow specifying existing CSR interface
2012-04-02 Sebastien Bourdeauducqfhdl: phase out pads
2012-04-02 Sebastien Bourdeauducqvpi: delete merged Icarus Verilog patch
2012-04-02 Sebastien Bourdeauducqfhdl/verilog: do not attempt to initialize instance...
2012-04-01 Sebastien Bourdeauducqbus/dfi: reset active low signals to 1
2012-04-01 Sebastien Bourdeauducqsim/proxy: support lists
2012-04-01 Sebastien Bourdeauducqfhdl/verilog: initialize internal read-only signals...
2012-03-31 Sebastien Bourdeauducqcorelogic/roundrobin: handle correctly special case...
2012-03-30 Sebastien Bourdeauducqbus/asmicon: initiator
2012-03-30 Sebastien Bourdeauducqsim: proxy
2012-03-23 Sebastien BourdeauducqUpdate copyright notices
2012-03-18 Sebastien Bourdeauducqcorelogic/fsm: typo
2012-03-17 Sebastien Bourdeauducqcorelogic/fsm: delayed enters
2012-03-16 Sebastien Bourdeauducqcorelogic/roundrobin: CE switching
2012-03-15 Sebastien Bourdeauducqcorelogic: convert timeline to function and move to...
2012-03-14 Sebastien Bourdeauducqbus/asmibus/hub: require finalization before get_slots
2012-03-14 Sebastien Bourdeauducqfhdl: export log2_int
2012-03-10 Alain Péteutsetup.py: simplify
2012-03-10 Sebastien Bourdeauducqdoc: more examples and comments
2012-03-10 Sebastien Bourdeauducqdoc: cosmetic changes (thanks sh4rm4 for reporting...
2012-03-09 Sebastien Bourdeauducqdoc: use script font
2012-03-09 Sebastien Bourdeauducqdoc: simulation
2012-03-09 Sebastien Bourdeauducqdoc: cosmetic changes (thanks rofl0r for reporting...
2012-03-09 Sebastien Bourdeauducqdoc: add logo
2012-03-09 Sebastien Bourdeauducqdoc: switch to sphinx
2012-03-08 Sebastien Bourdeauducqexamples: FIR filter simulation
2012-03-08 Sebastien Bourdeauducqfhdl: handle negative constants correctly
2012-03-08 Sebastien Bourdeauducqexamples: remove outdated wb_intercon simulation
2012-03-08 Sebastien Bourdeauducqvpi: support extra include directories
2012-03-08 Sebastien Bourdeauducqgitignore: update
2012-03-08 Sebastien Bourdeauducqbus: generic transaction model
2012-03-08 Sebastien Bourdeauducqvpi: patch for Icarus Verilog
2012-03-08 Sebastien Bourdeauducqexamples: small cleanup
2012-03-08 Sebastien Bourdeauducqsim: fix zero encoding
2012-03-08 Sebastien Bourdeauducqsim: fix message debug formatting
2012-03-06 Sebastien Bourdeauducqsim: make initialization cycle optional (selectable...
2012-03-06 Sebastien Bourdeauducqsim: memory access
2012-03-06 Sebastien Bourdeauducqfhdl: register memory objects with namespace
2012-03-06 Sebastien Bourdeauducqsim: support for signed numbers
2012-03-06 Sebastien Bourdeauducqfhdl/verilog: fix signed constant conversion
2012-03-06 Sebastien Bourdeauducqvpi: install target
2012-03-06 Sebastien Bourdeauducqsim: VCD generation
2012-03-06 Sebastien Bourdeauducqsim: clean startup/shutdown
2012-03-06 Sebastien Bourdeauducqsim: remove temporary files and socket
2012-03-06 Sebastien Bourdeauducqfhdl/namer: do not reference objects with __del__ metho...
2012-03-06 Sebastien Bourdeauducqsim: remove default sockaddr
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