yosys.git
2013-05-24 Clifford WolfFixed undef behavior in tests/asicworld/code_verilog_tu...
2013-05-24 Clifford WolfImproved FSM one-hot encoding, added binary encoding
2013-05-24 Clifford WolfAdded log_assert() api
2013-05-24 Clifford WolfAdded log_abort() api
2013-05-23 Clifford WolfFixed a gcc vs. clang determinism problem in abc pass
2013-05-23 Clifford WolfFixed memory corruption bug in opt_rmunused
2013-05-23 Clifford WolfOnly initialize TCL interpreter when needed
2013-05-23 Clifford WolfFixed memory leak in ilang frontend
2013-05-23 Clifford WolfAdded missing newline to some error messages
2013-05-23 Clifford WolfAdded labels to "help -write-tex-command-reference...
2013-05-23 Clifford WolfAdded support for processes to show command
2013-05-23 Clifford WolfFixed show command for constant assignments
2013-05-23 Clifford WolfSome improvements in opt_rmdff
2013-05-19 Clifford WolfMerge pull request #6 from hansiglaser/master
2013-05-19 Johann Glaseradded option '-Dname[=definition]' to command 'read_ver...
2013-05-17 Clifford WolfRemoved test cases that have been moved to yosys-test.
2013-05-17 Clifford WolfFixed to aggressive x-folding in opt_const
2013-05-16 Clifford WolfMerge branch 'master' of github.com:cliffordwolf/yosys
2013-05-16 Clifford WolfMerge branch 'bugfix'
2013-05-16 Clifford WolfFixed synthesis of functions in latched blocks
2013-05-14 Clifford WolfImproved vcdcd.pl (added -d option)
2013-05-14 Clifford WolfSome improvements in vcdcd.pl
2013-05-07 Clifford WolfAdded support for verilog === operator
2013-05-02 Clifford WolfAdded tcl "yosys -import" command
2013-05-01 Clifford WolfImproved/simplified TCL bindings
2013-04-27 Clifford WolfAdded support for const cell inputs in techmap
2013-04-27 Clifford WolfFixed README for new show command behavior (svg vs...
2013-04-26 Clifford WolfAdded "flatten" pass
2013-04-26 Clifford WolfFixed handling of positional module parameters
2013-04-26 Clifford WolfFixed hierarchy pass for hierarchies of parametric...
2013-04-26 Clifford WolfOnly use sha1 checksums for names of parametric modules...
2013-04-15 Clifford WolfFixed "show -format ..." command line parsing
2013-04-15 Clifford WolfAdded "submod -name ..." support
2013-04-13 Clifford WolfFixed a bug in AST frontend for cases with non-blocking...
2013-04-13 Clifford WolfFixed a bug in opt_const when optimizing 1-bit compares...
2013-04-07 Clifford WolfMerge branch 'master' of github.com:cliffordwolf/yosys
2013-04-07 Clifford WolfFixed clock related parameter names for $memrd and...
2013-04-05 Clifford WolfMerge pull request #5 from hansiglaser/master
2013-04-05 Johann Glaserfsm_export: optionally use binary state encoding as...
2013-04-05 Clifford WolfMerge pull request #4 from hansiglaser/master
2013-04-05 Johann Glaserfsm_export: specify KISS filename on command line
2013-04-01 Clifford WolfFixed/improved handling of colored wires in show command
2013-04-01 Clifford WolfAdded support for @<set-name> in expand select ops...
2013-04-01 Clifford WolfRemoved 4096 bytes limit for size of command from scrip...
2013-04-01 Clifford WolfAdded -color <color> <selection> option to show command
2013-03-31 Clifford WolfFixed "select" for "%%" stmt with emty stack
2013-03-31 Clifford WolfAdded "script" command
2013-03-31 Clifford WolfNow only use value from "initial" when no matching...
2013-03-31 Clifford WolfAdded AST_INITIAL (before verilog "initial" was mapped...
2013-03-31 Clifford WolfAdded test cases from 2012 paper on comparison of foss...
2013-03-31 Clifford WolfAdded k68 (m68k compatible cpu) test case from verilator
2013-03-29 Clifford WolfImproved opt_share for reduce cells
2013-03-29 Clifford WolfImproved opt_share for commutative standard cells
2013-03-28 Clifford WolfAdded EXTRA_TARGETS Makefile variable
2013-03-28 Clifford WolfImproved Makefile: Added ENABLE_* switches
2013-03-28 Clifford WolfImplemented TCL support (only via -c option at the...
2013-03-28 Clifford WolfImproved subcircuit verbose output (added portmapper...
2013-03-28 Clifford WolfFixed svgviewer hacks for builtin files
2013-03-28 Clifford WolfAdded proper TECHMAP_FAIL support and added support...
2013-03-28 Clifford WolfImplemented proper handling of stub placeholder modules
2013-03-27 Clifford WolfKeep viewport transform stable on reload in yosys-svgviewer
2013-03-27 Clifford WolfAdded check: only one module for "show" unless format...
2013-03-27 Clifford WolfNow using SVG and yosys-svgviewer per default in show...
2013-03-27 Clifford WolfAdded yosys-svgviewer to build system and renamed filte...
2013-03-27 Clifford WolfImported svgviewer from qt4.8
2013-03-26 Clifford WolfCreate nice errors when calling RTLIL::Module::derive...
2013-03-26 Clifford WolfCollect parameters in hierarchy -generate (and do nothi...
2013-03-26 Clifford WolfTiny bugfix in simlib.v
2013-03-26 Clifford WolfImprovements and bugfixes for generate blocks with...
2013-03-26 Clifford WolfFixed handling of unconditional generate blocks
2013-03-25 Clifford WolfAdded nosync attribute and some async reset related...
2013-03-25 Clifford WolfImproved verbose output of subcircuit
2013-03-25 Clifford WolfImproved method for finding fsm_expand candidates
2013-03-25 Clifford WolfAdded hierarchy -generate command for generating skelet...
2013-03-24 Clifford WolfChanged fsm_expand to merge multiplexers more aggressively
2013-03-24 Clifford WolfRenamed hansimem.v test case to mem_arst.v
2013-03-24 Clifford WolfFixed handling of show -viewer
2013-03-24 Clifford WolfFixed handling of internal signals in show command
2013-03-24 Clifford WolfImproved show -colors color assignments
2013-03-24 Clifford WolfAdded show -strech and renamed -widthlabels to -width
2013-03-24 Clifford WolfAdded -widthlabels options to chow command
2013-03-24 Clifford WolfAdded -notypes option to intersynth backend
2013-03-24 Clifford WolfReorganized TODOs
2013-03-24 Clifford WolfAdded mem2reg option to verilog frontend
2013-03-24 Clifford WolfFixed stdcells.v for $adff with undef reset value
2013-03-24 Clifford WolfAnother fix in mem2reg ast simplify logic
2013-03-24 Clifford WolfAdded -colors option to show command
2013-03-24 Clifford WolfAdded hansimem testcase (memory with async reset)
2013-03-24 Clifford WolfImproved mem2reg handling in ast simplifier
2013-03-23 Clifford WolfFixed gcc build (intersynth backend)
2013-03-23 Clifford WolfTiny fixes to verilog parser
2013-03-23 Clifford WolfVarious improvements in intersynth backend
2013-03-23 Clifford WolfAdded intersynth backend
2013-03-21 Clifford WolfAdded help -write-tex-command-reference-manual option
2013-03-21 Clifford WolfAdded eclipse CDT project files to .gitignore
2013-03-21 Clifford WolfAdded -S option for simple synthesis to gate logic
2013-03-21 Clifford WolfAvoid verilog-2k in verilog backend
2013-03-21 Clifford WolfDisabled the per-default dumping of ILANG code
2013-03-21 Clifford WolfAdded -nomap option to memory pass
2013-03-19 Clifford WolfMerge branch 'hansiglaser-master'
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