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microwatt.git
2020-08-06
Paul Mackerras
core: Implement the setb instruction
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2020-08-06
Paul Mackerras
core: Implement the mcrxrx instruction
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2020-08-05
Paul Mackerras
core: Implement the TAR register and the bctar instruction
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2020-08-05
Paul Mackerras
execute1: Use r.<field> not v.<field> in countzero...
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2020-08-05
Paul Mackerras
execute1: Take an extra cycle for OE=1 multiply instruc...
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2020-08-05
Paul Mackerras
multiplier: Generalize interface to the multiplier
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2020-07-22
Michael Neuling
Merge pull request #233 from paulusmack/master
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2020-07-20
Paul Mackerras
loadstore1: Better expression for store data formatting
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2020-07-20
Paul Mackerras
loadstore1: Further tweaks to improve synthesis with...
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2020-07-20
Paul Mackerras
dcache: Ease timing on wishbone data and byte selects
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2020-07-20
Paul Mackerras
decode1: Fix formatting
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2020-07-20
Paul Mackerras
loadstore1: Separate address calculation for MMU to...
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2020-07-20
Paul Mackerras
loadstore1: Generate busy signal earlier
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2020-07-20
Paul Mackerras
dcache: Output separate done-without-error and error...
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2020-07-20
Paul Mackerras
dcache: Ease timing on calculation of acks remaining
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2020-07-20
Paul Mackerras
dcache: Improve timing of valid/done outputs
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2020-07-14
Paul Mackerras
core: Don't generate logic for log data when LOG_LENGTH = 0
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2020-07-14
Paul Mackerras
countzero: Faster algorithm for count leading/trailing...
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2020-07-14
Paul Mackerras
MMU: Improve timing of done signal back to loadstore1
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2020-07-14
Paul Mackerras
dcache: Remove dependency of r1.wb.adr/dat/sel on...
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2020-07-14
Paul Mackerras
dcache: Update TLB PLRU one cycle later
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2020-07-14
Paul Mackerras
loadstore1: Eliminate two_dwords variable
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2020-07-14
Paul Mackerras
execute1: Ease timing on redirect_nia
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2020-07-14
Paul Mackerras
dcache: Do PLRU update one cycle later
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2020-07-14
Paul Mackerras
icache: Do PLRU update one cycle later
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2020-07-14
Michael Neuling
Merge pull request #232 from gromero/for-anton
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2020-07-13
Gustavo Romero
Enhance hello_world
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2020-07-09
Michael Neuling
Merge pull request #228 from ozbenh/misc
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2020-07-09
Michael Neuling
Merge pull request #222 from iamjpn/master
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2020-07-08
Jordan Niethe
tests: Add tests for the PVR
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2020-07-08
Benjamin Herrenschmidt
corefile/nexys_video: Parameter fixes
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2020-07-08
Benjamin Herrenschmidt
fpga: nexys-video: Wire up core_alt_reset
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2020-07-08
Benjamin Herrenschmidt
nexys_video: Fix nexys-video build
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2020-07-08
Benjamin Herrenschmidt
spi: Send dummy clocks at boot
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2020-07-08
Paul Mackerras
Merge pull request #223 from mikey/ecp5
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2020-07-07
Michael Neuling
Create github artifacts for ECP5 devices
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2020-07-07
Michael Neuling
Add PLL for ECP5 device
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2020-07-07
Anton Blanchard
Merge pull request #220 from mikey/ghdl-makefile
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2020-07-07
Anton Blanchard
Merge pull request #209 from mikey/yosys
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2020-07-07
Jordan Niethe
core: Implement PVR register
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2020-07-04
Michael Neuling
Use $(GHDL) rather than ghdl in Makefile
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2020-07-02
Michael Neuling
Add yosys/nextpnr ecp5 and verilog build to CI
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2020-07-02
Michael Neuling
Add FPGA_TARGET=ECP5-EVN make option for synthesis...
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2020-07-02
Michael Neuling
Add SYNTH_ECP5_FLAGS option for building
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2020-07-02
Michael Neuling
Add ram file to synthesis build dependencies
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2020-07-02
Michael Neuling
Add uart16550 files to yosys/nextpnr build
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2020-07-02
Michael Neuling
Add uart16550 files from fusesoc
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2020-07-02
Michael Neuling
Build to tmp file so nextpnr errors don't confuse make
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2020-07-02
Michael Neuling
Fix building with yosys/nextpnr
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2020-07-02
Michael Neuling
Add yosys builds files to gitignore
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2020-07-02
Michael Neuling
Send line feed if we get a carriage return in hello...
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2020-06-30
Michael Neuling
Merge pull request #216 from paulusmack/cfar
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2020-06-30
Paul Mackerras
Merge pull request #206 from Jbalkind/icachecleanup
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2020-06-29
Paul Mackerras
execute1: Do forwarding of the CR result to the next...
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2020-06-29
Paul Mackerras
execute1: Add latch to redirect path
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2020-06-29
Paul Mackerras
logical: Only do output inversion for OP_AND, OP_OR...
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2020-06-29
Paul Mackerras
core: Implement CFAR register
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2020-06-29
Michael Neuling
Merge pull request #213 from ozbenh/uart16550
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2020-06-29
Michael Neuling
Merge pull request #212 from ozbenh/liteeth
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2020-06-29
Michael Neuling
Merge pull request #214 from shingarov/fix-ld-target
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2020-06-26
Boris Shingarov
Fix ld error in elf maketarget
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2020-06-25
Benjamin Herrenschmidt
tests: Add updated micropython build with 16550 support
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2020-06-25
Benjamin Herrenschmidt
sim_console: Fix polling to check for POLLIN
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2020-06-25
Benjamin Herrenschmidt
uart: Make 16550 the default
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2020-06-23
Benjamin Herrenschmidt
syscon: Add flag to indicate the timebase frequency
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2020-06-23
Benjamin Herrenschmidt
console: Add support for the 16550 UART
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2020-06-23
Benjamin Herrenschmidt
uart: Add a simulation model for the 16550 compatible...
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2020-06-23
Benjamin Herrenschmidt
uart: Rename sim_uart.vhdl to sim_pp_uart.vhdl
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2020-06-23
Benjamin Herrenschmidt
console: Cleanup console API
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2020-06-23
Benjamin Herrenschmidt
uart: Import and hook up opencore 16550 compatible...
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2020-06-23
Benjamin Herrenschmidt
ex1: Add SPR_TBU support
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2020-06-23
Benjamin Herrenschmidt
liteeth: Hook up LiteX LiteEth ethernet controller
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2020-06-23
Michael Neuling
Merge pull request #211 from shenki/spi-constraint
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2020-06-23
Joel Stanley
spi: Fix dat_i_l constraints
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2020-06-23
Michael Neuling
Merge pull request #210 from ozbenh/xics
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2020-06-22
Benjamin Herrenschmidt
xics: Add support for reduced priority field size
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2020-06-19
Benjamin Herrenschmidt
xics: Add simple ICS
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2020-06-19
Benjamin Herrenschmidt
xics/icp: MFRR starts at 0xff not 0x00
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2020-06-19
Benjamin Herrenschmidt
tests/xics: Ensure no compiler optimisations in delay()
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2020-06-19
Benjamin Herrenschmidt
xics: ICP should be big endian !
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2020-06-19
Benjamin Herrenschmidt
tests: Fix Makefile.test to not allow host includes
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2020-06-19
Michael Neuling
Merge pull request #208 from paulusmack/faster
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2020-06-17
Paul Mackerras
Merge pull request #207 from ozbenh/misc
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2020-06-16
Paul Mackerras
fpga: Add a xilinx_specific fileset to microwatt.core
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2020-06-16
Paul Mackerras
Make LOG_LENGTH configurable per FPGA variant
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2020-06-15
Paul Mackerras
execute1: Reduce width of the result mux to help timing
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2020-06-15
Paul Mackerras
core: Implement a simple branch predictor
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2020-06-15
Paul Mackerras
decode1: Improve timing for slow SPR decode path
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2020-06-14
Paul Mackerras
decode1: Add a stash buffer to the output
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2020-06-14
Benjamin Herrenschmidt
soc: Slight cleanup of IRQ assignments
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2020-06-14
Benjamin Herrenschmidt
soc: Rename uart_dat8 to uart0_dat8
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2020-06-14
Benjamin Herrenschmidt
soc: Rename wb_dram_ctrl to wb_ext_io and rework decoding
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2020-06-13
Jonathan Balkind
Minor refactor of icache to make less dependent on...
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2020-06-13
Paul Mackerras
dcache: Reduce back-to-back store latency from 3 cycles...
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2020-06-13
Benjamin Herrenschmidt
soc: Don't require dram wishbones signals to be wired...
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2020-06-13
Benjamin Herrenschmidt
soc: Add defaults for some input signals
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2020-06-13
Benjamin Herrenschmidt
soc: Remove unused RESET_LOW generic
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2020-06-13
Paul Mackerras
mmu: Take an extra cycle to do TLB invalidations
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2020-06-13
Paul Mackerras
dcache: Reduce latencies and improve timing
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2020-06-13
Paul Mackerras
decode: Work out ispr1/ispr2 in parallel with decode...
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