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yosys.git
2014-07-27
Clifford Wolf
Added conversion from ObjRange to std::vector and std...
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2014-07-27
Clifford Wolf
Added RTLIL::ObjIterator and RTLIL::ObjRange
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2014-07-27
Clifford Wolf
Using std::move() in SigSpec move constructor
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2014-07-27
Clifford Wolf
Added RTLIL::SigSpec move constructor and move assignme...
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2014-07-27
Clifford Wolf
Mostly cosmetic changes to rtlil.h
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2014-07-26
Clifford Wolf
Refactoring: Renamed RTLIL::Module::cells to cells_
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2014-07-26
Clifford Wolf
Refactoring: Renamed RTLIL::Module::wires to wires_
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2014-07-26
Clifford Wolf
New message for completion of build
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2014-07-26
Clifford Wolf
Changed more code to the new RTLIL::Wire constructors
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2014-07-26
Clifford Wolf
Changed a lot of code to the new RTLIL::Wire constructors
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2014-07-26
Clifford Wolf
Added tests/various/.gitignore
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2014-07-26
Clifford Wolf
Added tests/various/submod_extract.ys
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2014-07-26
Clifford Wolf
Added support for here documents
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2014-07-26
Clifford Wolf
More RTLIL::Cell API usage cleanups
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2014-07-26
Clifford Wolf
Added RTLIL::Cell::has(portname)
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2014-07-26
Clifford Wolf
Merge automatic and manual code changes for new cell...
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2014-07-26
Clifford Wolf
Manual fixes for new cell connections API
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2014-07-26
Clifford Wolf
Changed users of cell->connections_ to the new API...
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2014-07-26
Clifford Wolf
Added some missing "const" in rtlil.h
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2014-07-26
Clifford Wolf
Added RTLIL::Module::connections()
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2014-07-26
Clifford Wolf
Added RTLIL::Module::connect(const RTLIL::SigSig&)
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2014-07-26
Clifford Wolf
Use "wget -N" in tests/vloghtb/run-test.sh
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2014-07-26
Clifford Wolf
Added "passed" message to make test targets
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2014-07-26
Clifford Wolf
Automatically pack SigSpec on copy/assign
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2014-07-26
Clifford Wolf
Added new RTLIL::Cell port access methods
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2014-07-26
Clifford Wolf
Renamed RTLIL::{Module,Cell}::connections to connections_
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2014-07-26
Clifford Wolf
Cosmetic fixes for "make abc"
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2014-07-26
Clifford Wolf
Added "Checklist for adding internal cell types"
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2014-07-25
Clifford Wolf
Added copy-constructor-like module->addCell(name, other...
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2014-07-25
Clifford Wolf
Use only module->addCell() and module->remove() to...
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2014-07-25
Clifford Wolf
Various RTLIL::SigSpec related code cleanups
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2014-07-25
Clifford Wolf
Added RTLIL::SigSpec is_chunk()/as_chunk() API
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2014-07-25
Clifford Wolf
Added "make vgtest"
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2014-07-25
Clifford Wolf
Fixed two memory leaks in ast simplify
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2014-07-25
Clifford Wolf
Renamed some of the test cases in tests/simple to avoid...
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2014-07-25
Clifford Wolf
Fixed memory corruption in "opt_reduce" pass
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2014-07-25
Clifford Wolf
Disabled cover() for non-linux builds
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2014-07-25
Clifford Wolf
Added more stuff to checklist
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2014-07-25
Clifford Wolf
Updated verific build/test instructions
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2014-07-25
Clifford Wolf
Improvements in "cover" command
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2014-07-25
Clifford Wolf
Removed Minisat dependency on zlib
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2014-07-25
Clifford Wolf
Added more stuff to the checklist
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2014-07-25
Clifford Wolf
Fixed typo in cover id
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2014-07-25
Clifford Wolf
Added "make clean-abc"
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2014-07-25
Clifford Wolf
Further improved "make" prettiness
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2014-07-24
Clifford Wolf
Replaced more old SigChunk programming patterns
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2014-07-24
Clifford Wolf
Updated ABC to hg id "b1e63d18768d"
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2014-07-24
Clifford Wolf
Added cover() calls to opt_const
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2014-07-24
Clifford Wolf
Added cover_list() API
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2014-07-24
Clifford Wolf
Added "make SMALL=1"
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2014-07-24
Clifford Wolf
Now "make PRETTY=1" is the default setting
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2014-07-24
Clifford Wolf
Added percentage display to "make PRETTY=1"
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2014-07-24
Clifford Wolf
Added "make PRETTY=1"
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2014-07-24
Clifford Wolf
Added "cover" command
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2014-07-24
Clifford Wolf
Some improvements in SigSpec packing/unpacking and...
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2014-07-24
Clifford Wolf
Now using a dedicated ELF section for all coverage...
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2014-07-24
Clifford Wolf
Small changes regarding cover() and check() in SigSpec
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2014-07-24
Clifford Wolf
Renamed RELEASE_CHECKLIST -> CHECKLIST
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2014-07-24
Clifford Wolf
Added support for YOSYS_COVER_FILE env variable
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2014-07-24
Clifford Wolf
Added cover() calls to RTLIL::SigSpec methods
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2014-07-24
Clifford Wolf
Added support for YOSYS_COVER_DIR env variable
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2014-07-24
Clifford Wolf
Added cover() API
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2014-07-24
Clifford Wolf
Added RELEASE_CHECKLIST
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2014-07-24
Clifford Wolf
Added "make config-gcc-4.7"
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2014-07-24
Clifford Wolf
Added "make vloghtb"
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2014-07-23
Clifford Wolf
Added hashing to RTLIL::SigSpec relational and equal...
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2014-07-23
Clifford Wolf
Disabled RTLIL::SigSpec::check() in release builds
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2014-07-23
Clifford Wolf
Fixed release build
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2014-07-23
Clifford Wolf
Various fixes in Verific frontend for new RTLIL API
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2014-07-23
Clifford Wolf
Added RTLIL::SigSpec::repeat()
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2014-07-23
Clifford Wolf
Various small fixes (from gcc compiler warnings)
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2014-07-23
Clifford Wolf
Removed RTLIL::SigSpec::optimize()
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2014-07-23
Clifford Wolf
Turned RTLIL::SigSpec::optimize() to a no-op: a packed...
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2014-07-23
Clifford Wolf
Fixed manual/CHAPTER_Prog/stubnets.cc
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2014-07-23
Clifford Wolf
Removed RTLIL::SigSpec::expand() method
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2014-07-23
Clifford Wolf
Added eclipse .setting folder to .gitignore
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2014-07-23
Clifford Wolf
Fixed all users of SigSpec::chunks_rw() and removed it
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2014-07-23
Clifford Wolf
Replaced RTLIL::SigSpec::operator!=() with inline version
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2014-07-23
Clifford Wolf
Merge branch: Refactoring {SigSpec|SigChunk}(RTLIL...
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2014-07-23
Clifford Wolf
Refactoring {SigSpec|SigChunk}(RTLIL::Wire *wire, ...
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2014-07-23
Clifford Wolf
Refactoring {SigSpec|SigChunk}(RTLIL::Wire *wire, ...
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2014-07-23
Clifford Wolf
Refactoring {SigSpec|SigChunk}(RTLIL::Wire *wire, ...
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2014-07-23
Clifford Wolf
Some cleanups in RTLIL::SigChunk::SigChunk(const RTLIL...
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2014-07-22
Clifford Wolf
SigSpec refactoring: More cleanups of old SigSpec use...
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2014-07-22
Clifford Wolf
SigSpec refactoring: Added RTLIL::SigSpecIterator
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2014-07-22
Clifford Wolf
SigSpec refactoring: cleanup of old SigSpec usage in...
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2014-07-22
Clifford Wolf
Fixed memory corruption with new SigSpec API in proc_mux
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2014-07-22
Clifford Wolf
SigSpec refactoring: added RTLIL::SigSpec::operator[]
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2014-07-22
Clifford Wolf
fixed memory leak in fsm_opt
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2014-07-22
Clifford Wolf
SigSpec refactoring: rewrote some RTLIL::SigSpec method...
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2014-07-22
Clifford Wolf
Removed RTLIL::SigChunk::compare()
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2014-07-22
Clifford Wolf
SigSpec refactoring: added RTLIL::SigSpec::bits() and...
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2014-07-22
Clifford Wolf
SigSpec refactoring: change RTLIL::SigSpec::chunks...
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2014-07-22
Clifford Wolf
SigSpec refactoring: change RTLIL::SigSpec::size()...
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2014-07-22
Clifford Wolf
SigSpec refactoring: using the accessor functions every...
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2014-07-22
Clifford Wolf
SigSpec refactoring: renamed the SigSpec members to...
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2014-07-22
Clifford Wolf
SigSpec refactoring: renamed chunks and width to __chun...
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2014-07-22
Clifford Wolf
Fixed ilang parsing of process attributes
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2014-07-22
Clifford Wolf
Fixed make rules for ilang parser
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2014-07-21
Clifford Wolf
Use "opt -fine" in test/vloght/test_mapopt.sh
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