nmigen.git
2019-08-19 whitequarkREADME: fix typos.
2019-08-19 whitequarkhdl.cd: implement local clock domains.
2019-08-19 whitequarkback.pysim: index domains by identity, not by name.
2019-08-19 whitequarkhdl.xfrm: lower resets in DomainLowerer as well.
2019-08-19 whitequarkhdl.xfrm: consider fragment's own domains in DomainLowerer.
2019-08-19 whitequarkformal→asserts
2019-08-19 whitequarktracer: fix typo.
2019-08-19 whitequarkbuild.plat: do not prepare fragments twice.
2019-08-19 whitequarkback.{rtlil,verilog}: split convert_fragment() off...
2019-08-18 Robin Heinemannbuild.dsl: add conn argument to Connector.
2019-08-18 whitequarkcompat.fhdl.decorators: avoid using deprecated NativeCE...
2019-08-18 whitequarkhdl.xfrm: make deprecated CEInserter more well-behaved.
2019-08-15 whitequarkhdl.ast: implement Initial.
2019-08-15 whitequarkhdl.xfrm: sample cache should be per-fragment.
2019-08-12 whitequarkhdl.xfrm: CEInserter→EnableInserter.
2019-08-08 whitequarkhdl.ast: hash-cons ValueKey.
2019-08-08 whitequarktracer: use sys._getframe directly.
2019-08-08 whitequarkcompat.fhdl.decorators: port from oMigen.
2019-08-08 whitequarkcompat.fhdl.module: fix finalization of transformed...
2019-08-07 whitequarkvendor.lattice_ice40: add iCE5LP2K support.
2019-08-07 whitequarkvendor.lattice_ice40: add iCE40UP3K support.
2019-08-07 whitequarkvendor.lattice_ice40: add iCE5LP1K support.
2019-08-04 whitequarkvendor.xilinx_{spartan_3_6,7series}: reconsider default...
2019-08-04 whitequarkvendor.xilinx_spartan_3_6: reconsider bitgen defaults.
2019-08-04 whitequarkvendor.xilinx_spartan_3_6: set bitgen defaults to ...
2019-08-04 whitequarkvendor.xilinx_spartan_3_6: always use -w for map/par...
2019-08-04 whitequarkvendor.xilinx_spartan_3_6: do not use retiming by default.
2019-08-04 whitequarkvendor.xilinx_spartan_3_6: force use of bash on UNIX.
2019-08-04 whitequarkbuild.plat: allow selecting a specific UNIX shell inter...
2019-08-04 whitequarkvendor.lattice_ice40: avoid routing conflicts with...
2019-08-04 whitequarkback.rtlil: use a dummy wire, not 'x, when assigning...
2019-08-03 whitequarkback.rtlil: actually match shape of left hand side.
2019-08-03 whitequarkvendor.lattice_ice40: add missing signal indexing.
2019-08-03 whitequarkbuild.run: use keyword-only arguments where appropriate.
2019-08-03 whitequarkcompat.fhdl.specials: track changes in build.plat.
2019-08-03 whitequarkhdl.dsl: reword m.If(~True) warning to be more clear.
2019-08-03 whitequarkbuild.plat,vendor: automatically create sync domain...
2019-08-03 whitequarkhdl.ir: allow adding more than one domain in missing...
2019-08-03 whitequarkhdl.ir: don't expose as ports missing domains added...
2019-08-03 whitequarkbuild.plat: add default_rst, to be used with default_clk.
2019-08-03 whitequarkbuild.plat: add default_clk{,_constraint,_frequency}.
2019-08-03 whitequarkhdl.ir: allow returning elaboratables from missing...
2019-08-03 whitequarkhdl.ir: raise DomainError if a domain is used but not...
2019-08-03 whitequarkhdl.ir: call back from Fragment.prepare if a clock...
2019-08-03 whitequarkhdl.dsl: warn on suspicious statements like `m.If(...
2019-08-03 whitequarkImprove test added in 29fee01f to not leak warnings.
2019-08-03 whitequarkback.rtlil: fix sim-synth mismatch with assigns followi...
2019-08-03 whitequarkhdl.ast: fix typo.
2019-08-03 whitequarkhdl.ast: deprecate Value.part, add Value.{bit,word...
2019-08-03 whitequarkhdl.ast, back.rtlil: add source locations to anonymous...
2019-08-03 whitequarkhdl.ir: warn if .elaborate() returns None.
2019-07-31 whitequarkhdl.xfrm: handle mem.{Read,Write}Port in CEInserter.
2019-07-21 N. Engelhardtvendor: don't emit duplicate iobuf submodule names.
2019-07-19 N. Engelhardthdl.dsl: add getters to m.submodules.
2019-07-15 Alain Péteutlib.fifo: fix typo.
2019-07-14 Staf VerhaegenPin: Add extra hierarchy level for name derivation
2019-07-14 William D.... build.run: Ensure batch script returns proper error...
2019-07-12 whitequarkback.pysim: correctly add gtkwave traces for signals...
2019-07-10 William D.... build.dsl: Add optional name_suffix to Resource.family.
2019-07-10 whitequarkback.pysim: avoid malformed VCD files when a decoder...
2019-07-10 whitequarkhdl.ir: make UnusedElaboratable a real warning.
2019-07-09 whitequarkback.rtlil: add decodings to cases when switching on...
2019-07-09 whitequarkback.verilog: run proc_prune for much cleaner output.
2019-07-09 whitequarkhdl.{ast,dsl},back.rtlil: track source locations for...
2019-07-09 Jacob Lifshaytracer: add PyPy support to get_var_name().
2019-07-09 whitequarkbuild.dsl: add Resource.family abstraction.
2019-07-08 whitequarkbuild.{dsl,res}: allow platform-dependent attributes...
2019-07-08 whitequarkhdl.rec: respect modifications to signals in Record...
2019-07-08 whitequarkback.rtlil: don't name-prefix signals connected to...
2019-07-08 whitequarkbuild.{dsl,res}: allow removing attributes from subsignals.
2019-07-08 whitequarkbuild.dsl: allow assertions on subsignal widths.
2019-07-08 whitequarkhdl.{ast,cd,dsl,xfrm}: reject inappropriately used...
2019-07-08 whitequarktest: fix Travis.
2019-07-08 whitequarktest: generate examples to verilog as part of unit...
2019-07-08 whitequarkexamples/basic/ctr_ce: fix outdated syntax.
2019-07-08 whitequarkcompat.genlib.fsm: fix after commit dac62754.
2019-07-08 whitequarkhdl.xfrm: don't overwrite source locations on ClockDoma...
2019-07-08 whitequarkhdl.{dsl,mem,xfrm}: inject appropriate source locations.
2019-07-08 whitequarkback.rtlil: ignore empty source locations.
2019-07-08 whitequarkhdl.ast: use keyword-only arguments as appropriate.
2019-07-08 whitequarkback.rtlil: attach source locations to switches, not...
2019-07-08 whitequarkback.rtlil: use a more principled approach to attribute...
2019-07-07 Alain Péteutvendor.xilinx_7series: generate also binary bitfile.
2019-07-07 William D.... vendor.xilinx_spartan_3_6: Add Spartan3A family support.
2019-07-07 whitequarkvendor.lattice_ecp5: don't leave LUT inputs disconnected.
2019-07-07 whitequarkhdl.dsl: further clarify error message for incorrect...
2019-07-07 whitequarkhdl.dsl: clarify error message for incorrect nesting.
2019-07-07 whitequarkhdl.dsl: gracefully handle FSM with no states.
2019-07-07 whitequarkbuild.plat: source a script with toolchain environment.
2019-07-07 whitequarkbuild.run: only use os.path on the target OS.
2019-07-07 whitequarkbuild.run: make BuildProducts abstract, add LocalBuildP...
2019-07-06 whitequarkbuild.plat, vendor.*: don't join strings passed as...
2019-07-06 whitequarkbuild.run: make sure BuildProducts._root is not easily...
2019-07-04 Staf Verhaegenvendor.xilinx_{7series,spartan6}: Support extra VHDL...
2019-07-03 whitequarkhdl.dsl: fix src_loc_at for FSM state signal.
2019-07-03 whitequarkback.rtlil: emit \src attributes for processes via...
2019-07-03 whitequarkhdl.ast: fix src_loc_at for Mux().
2019-07-03 whitequarkbuild.res: detect physical conflicts earlier.
2019-07-03 whitequarkhdl.rec: thread src_loc_at to all inner Signals and...
2019-07-03 whitequarkvendor: give names to IO buffer instances.
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