| 2014-08-01 |
Clifford Wolf | Added ModIndex helper class, some changes to RTLIL... |
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| 2014-08-01 |
Clifford Wolf | Packed SigBit::data and SigBit::offset in a union |
commit | commitdiff | tree |
| 2014-08-01 |
Clifford Wolf | Consolidated hana test benches into fewer files |
commit | commitdiff | tree |
| 2014-08-01 |
Clifford Wolf | Added "test_autotb -n <num_iter>" option |
commit | commitdiff | tree |
| 2014-07-31 |
Clifford Wolf | Renamed modwalker.h to modtools.h |
commit | commitdiff | tree |
| 2014-07-31 |
Clifford Wolf | Various cleanups in Makefile, Renamed default configura... |
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| 2014-07-31 |
Clifford Wolf | Added compiler + compiler version + compiler flags... |
commit | commitdiff | tree |
| 2014-07-31 |
Clifford Wolf | Fixed build of verific bindings |
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| 2014-07-31 |
Clifford Wolf | Renamed port access function on RTLIL::Cell, added... |
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| 2014-07-31 |
Clifford Wolf | Added "trace" command |
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| 2014-07-31 |
Clifford Wolf | Added RTLIL::Monitor |
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| 2014-07-31 |
Clifford Wolf | Added module->design and cell->module, wire->module... |
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| 2014-07-31 |
Clifford Wolf | Moved some stuff to kernel/yosys.{h,cc}, using Yosys... |
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| 2014-07-31 |
Clifford Wolf | Renamed "stdcells.v" to "techmap.v" |
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| 2014-07-31 |
Clifford Wolf | Added "techmap -assert" |
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| 2014-07-31 |
Clifford Wolf | Reorganized stdcells.v (no actual code change, just... |
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| 2014-07-30 |
Clifford Wolf | Added "yosys -A" |
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| 2014-07-30 |
Clifford Wolf | Added "yosys -Q" |
commit | commitdiff | tree |
| 2014-07-30 |
Clifford Wolf | Added techmap CONSTMAP feature |
commit | commitdiff | tree |
| 2014-07-30 |
Clifford Wolf | Fixed counting verilog line numbers for "// synopsys... |
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| 2014-07-30 |
Clifford Wolf | Added write_file command |
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| 2014-07-30 |
Clifford Wolf | Added "make -j{N}" support to "make test" |
commit | commitdiff | tree |
| 2014-07-30 |
Clifford Wolf | Improvements in test_cell |
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| 2014-07-30 |
Clifford Wolf | New techmap default rules for $shr $sshr $shl $sshl |
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| 2014-07-30 |
Clifford Wolf | Using native ezSAT shift ops in satgen, fixed $shift... |
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| 2014-07-30 |
Clifford Wolf | Added native support for shift operations to ezSAT |
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| 2014-07-30 |
Clifford Wolf | Added "log_dump_val_worker(char *v)" |
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| 2014-07-30 |
Clifford Wolf | Added CodingStyle document |
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| 2014-07-30 |
Clifford Wolf | Added "kernel/yosys.h" and "kernel/yosys.cc" |
commit | commitdiff | tree |
| 2014-07-29 |
Clifford Wolf | Added "test_cell" command |
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| 2014-07-29 |
Clifford Wolf | Renamed "write_autotest" to "test_autotb" and moved... |
commit | commitdiff | tree |
| 2014-07-29 |
Clifford Wolf | Fixed Verilog pre-processor for files with no trailing... |
commit | commitdiff | tree |
| 2014-07-29 |
Clifford Wolf | Bugfix in simlib.v for iverilog |
commit | commitdiff | tree |
| 2014-07-29 |
Clifford Wolf | Allow "hierarchy -generate" for $__ cells |
commit | commitdiff | tree |
| 2014-07-29 |
Clifford Wolf | Added "techmap -map %{design-name}" |
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| 2014-07-29 |
Clifford Wolf | Added $shift and $shiftx cell types (needed for correct... |
commit | commitdiff | tree |
| 2014-07-28 |
Clifford Wolf | Removed left over debug code |
commit | commitdiff | tree |
| 2014-07-28 |
Clifford Wolf | Fixed part selects of parameters |
commit | commitdiff | tree |
| 2014-07-28 |
Clifford Wolf | Set results of out-of-bounds static bit/part select... |
commit | commitdiff | tree |
| 2014-07-28 |
Clifford Wolf | Fixed RTLIL code generator for part select of parameter |
commit | commitdiff | tree |
| 2014-07-28 |
Clifford Wolf | Fixed width detection for part selects |
commit | commitdiff | tree |
| 2014-07-28 |
Clifford Wolf | Added support for "upto" wires to Verilog front- and... |
commit | commitdiff | tree |
| 2014-07-28 |
Clifford Wolf | Added wire->upto flag for signals such as "wire [0... |
commit | commitdiff | tree |
| 2014-07-28 |
Clifford Wolf | Using log_assert() instead of assert() |
commit | commitdiff | tree |
| 2014-07-28 |
Clifford Wolf | Added std::initializer_list<> constructor to SigSpec |
commit | commitdiff | tree |
| 2014-07-28 |
Clifford Wolf | Added cover() to all SigSpec constructors |
commit | commitdiff | tree |
| 2014-07-28 |
Clifford Wolf | Fixed signdness detection of expressions with bit-... |
commit | commitdiff | tree |
| 2014-07-28 |
Clifford Wolf | Improvements in tests/vloghtb |
commit | commitdiff | tree |
| 2014-07-27 |
Clifford Wolf | Added techmap -extern |
commit | commitdiff | tree |
| 2014-07-27 |
Clifford Wolf | Added proper Design->addModule interface |
commit | commitdiff | tree |
| 2014-07-27 |
Clifford Wolf | Added topological sorting to techmap |
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| 2014-07-27 |
Clifford Wolf | Added SigPool::check(bit) |
commit | commitdiff | tree |
| 2014-07-27 |
Clifford Wolf | Small improvements in PerformanceTimer API |
commit | commitdiff | tree |
| 2014-07-27 |
Clifford Wolf | Fixed bug in opt_clean |
commit | commitdiff | tree |
| 2014-07-27 |
Clifford Wolf | Improved performance of opt_const on large modules |
commit | commitdiff | tree |
| 2014-07-27 |
Clifford Wolf | Added RTLIL::SigSpec::remove_const() handling of packed... |
commit | commitdiff | tree |
| 2014-07-27 |
Clifford Wolf | Added RTLIL::SigSpecConstIterator |
commit | commitdiff | tree |
| 2014-07-27 |
Clifford Wolf | Fixed a bug in opt_clean and some RTLIL API usage cleanups |
commit | commitdiff | tree |
| 2014-07-27 |
Clifford Wolf | Added log_cmd_error_expection |
commit | commitdiff | tree |
| 2014-07-27 |
Clifford Wolf | Fixed verific bindings for new RTLIL api |
commit | commitdiff | tree |
| 2014-07-27 |
Clifford Wolf | Fixed ilang parser for new RTLIL API |
commit | commitdiff | tree |
| 2014-07-27 |
Clifford Wolf | Using new obj iterator API in a few places |
commit | commitdiff | tree |
| 2014-07-27 |
Clifford Wolf | Added RTLIL::Module::wire(id) and cell(id) lookup functions |
commit | commitdiff | tree |
| 2014-07-27 |
Clifford Wolf | Added RTLIL::Design::modules() |
commit | commitdiff | tree |
| 2014-07-27 |
Clifford Wolf | Refactoring: Renamed RTLIL::Design::modules to modules_ |
commit | commitdiff | tree |
| 2014-07-27 |
Clifford Wolf | Added conversion from ObjRange to std::vector and std... |
commit | commitdiff | tree |
| 2014-07-27 |
Clifford Wolf | Added RTLIL::ObjIterator and RTLIL::ObjRange |
commit | commitdiff | tree |
| 2014-07-27 |
Clifford Wolf | Using std::move() in SigSpec move constructor |
commit | commitdiff | tree |
| 2014-07-27 |
Clifford Wolf | Added RTLIL::SigSpec move constructor and move assignme... |
commit | commitdiff | tree |
| 2014-07-27 |
Clifford Wolf | Mostly cosmetic changes to rtlil.h |
commit | commitdiff | tree |
| 2014-07-26 |
Clifford Wolf | Refactoring: Renamed RTLIL::Module::cells to cells_ |
commit | commitdiff | tree |
| 2014-07-26 |
Clifford Wolf | Refactoring: Renamed RTLIL::Module::wires to wires_ |
commit | commitdiff | tree |
| 2014-07-26 |
Clifford Wolf | New message for completion of build |
commit | commitdiff | tree |
| 2014-07-26 |
Clifford Wolf | Changed more code to the new RTLIL::Wire constructors |
commit | commitdiff | tree |
| 2014-07-26 |
Clifford Wolf | Changed a lot of code to the new RTLIL::Wire constructors |
commit | commitdiff | tree |
| 2014-07-26 |
Clifford Wolf | Added tests/various/.gitignore |
commit | commitdiff | tree |
| 2014-07-26 |
Clifford Wolf | Added tests/various/submod_extract.ys |
commit | commitdiff | tree |
| 2014-07-26 |
Clifford Wolf | Added support for here documents |
commit | commitdiff | tree |
| 2014-07-26 |
Clifford Wolf | More RTLIL::Cell API usage cleanups |
commit | commitdiff | tree |
| 2014-07-26 |
Clifford Wolf | Added RTLIL::Cell::has(portname) |
commit | commitdiff | tree |
| 2014-07-26 |
Clifford Wolf | Merge automatic and manual code changes for new cell... |
commit | commitdiff | tree |
| 2014-07-26 |
Clifford Wolf | Manual fixes for new cell connections API |
commit | commitdiff | tree |
| 2014-07-26 |
Clifford Wolf | Changed users of cell->connections_ to the new API... |
commit | commitdiff | tree |
| 2014-07-26 |
Clifford Wolf | Added some missing "const" in rtlil.h |
commit | commitdiff | tree |
| 2014-07-26 |
Clifford Wolf | Added RTLIL::Module::connections() |
commit | commitdiff | tree |
| 2014-07-26 |
Clifford Wolf | Added RTLIL::Module::connect(const RTLIL::SigSig&) |
commit | commitdiff | tree |
| 2014-07-26 |
Clifford Wolf | Use "wget -N" in tests/vloghtb/run-test.sh |
commit | commitdiff | tree |
| 2014-07-26 |
Clifford Wolf | Added "passed" message to make test targets |
commit | commitdiff | tree |
| 2014-07-26 |
Clifford Wolf | Automatically pack SigSpec on copy/assign |
commit | commitdiff | tree |
| 2014-07-26 |
Clifford Wolf | Added new RTLIL::Cell port access methods |
commit | commitdiff | tree |
| 2014-07-26 |
Clifford Wolf | Renamed RTLIL::{Module,Cell}::connections to connections_ |
commit | commitdiff | tree |
| 2014-07-26 |
Clifford Wolf | Cosmetic fixes for "make abc" |
commit | commitdiff | tree |
| 2014-07-26 |
Clifford Wolf | Added "Checklist for adding internal cell types" |
commit | commitdiff | tree |
| 2014-07-25 |
Clifford Wolf | Added copy-constructor-like module->addCell(name, other... |
commit | commitdiff | tree |
| 2014-07-25 |
Clifford Wolf | Use only module->addCell() and module->remove() to... |
commit | commitdiff | tree |
| 2014-07-25 |
Clifford Wolf | Various RTLIL::SigSpec related code cleanups |
commit | commitdiff | tree |
| 2014-07-25 |
Clifford Wolf | Added RTLIL::SigSpec is_chunk()/as_chunk() API |
commit | commitdiff | tree |
| 2014-07-25 |
Clifford Wolf | Added "make vgtest" |
commit | commitdiff | tree |
| 2014-07-25 |
Clifford Wolf | Fixed two memory leaks in ast simplify |
commit | commitdiff | tree |
| 2014-07-25 |
Clifford Wolf | Renamed some of the test cases in tests/simple to avoid... |
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