yosys.git
2013-12-04 Clifford WolfAdded sincos test case
2013-12-04 Clifford WolfAdded support for local regs in named blocks
2013-12-04 Clifford WolfFixed gentb_constant handling in autotest backend
2013-12-04 Clifford WolfMore ABC releated Makefile changes
2013-12-03 Clifford WolfMinor improvements in ABc build
2013-12-02 Clifford WolfProgress on AppNote 011
2013-12-02 Clifford WolfFixed submod for non-primitive cells
2013-12-02 Clifford WolfFixed submod for non-cleaned designs
2013-12-02 Clifford WolfAdded Pass:call_newsel API
2013-12-02 Clifford WolfAdded "history" command
2013-12-01 Clifford WolfA fix in memory_dff for write ports with static addresses
2013-12-01 Clifford WolfProgress on AppNote 011
2013-11-29 Clifford WolfProgress on AppNote 011
2013-11-29 Clifford WolfProgress on AppNote 011
2013-11-29 Clifford WolfUsing RTLIL::id2cstr for prompt printing
2013-11-29 Clifford WolfAdded dump -m and -n options
2013-11-28 Clifford WolfProgress on AppNote 011
2013-11-28 Clifford WolfMerge pull request #17 from mschmoelzer/master
2013-11-28 Clifford WolfFixed temp net name generation in rtlil process generat...
2013-11-28 Clifford WolfAdded pattern support to "ls" command
2013-11-28 Clifford WolfImproved ID matching scheme in select (and thus for...
2013-11-28 Clifford WolfFixes and improvements in "show" command
2013-11-28 Martin SchmölzerInclude unistd.h in svgview.cpp (required for getcwd...
2013-11-28 Clifford WolfMore progress on AppNote 011
2013-11-28 Clifford WolfAdded "src" attribute to processes
2013-11-28 Clifford WolfStarted writing appnote 011
2013-11-28 Clifford WolfAdded support for "show -pause" and "show -format dot"
2013-11-28 Clifford WolfAdded QGraphicsWebView to yosys-svgviewer
2013-11-27 Clifford WolfUpdated ABC to 9241719523f6
2013-11-27 Clifford WolfAdded some svgviewer code for possible future switch...
2013-11-27 Clifford WolfMerge branch 'master' of github.com:cliffordwolf/yosys
2013-11-27 Clifford WolfTighter integration of ABC build
2013-11-27 Clifford WolfSet version number to 0.1.0+
2013-11-25 Clifford WolfStarted implementing undef support in "sat" command
2013-11-25 Clifford WolfBugfixes in new "stat" command
2013-11-25 Clifford WolfAdded "stat" command
2013-11-25 Clifford WolfImprovements in satgen undef handling
2013-11-25 Clifford WolfImprovements in satgen undef handling
2013-11-25 Clifford WolfAdded ezsat vec_const() api
2013-11-25 Clifford WolfStarted implementing undef handling in satgen
2013-11-25 Clifford WolfRemoved undef feature from ezsat api
2013-11-24 Clifford WolfUsing simplemap mappers from techmap
2013-11-24 Clifford WolfAdded simplemap pass
2013-11-24 Clifford WolfRenamed stdcells_sim.v to simcells.v and fixed blackbox.v
2013-11-24 Clifford WolfAdded module->avail_parameters (for advanced techmap...
2013-11-24 Clifford WolfAdded techmap -D and -I options
2013-11-24 Clifford WolfAdded verilog frontend -ignore_redef option
2013-11-24 Clifford WolfAdded "techmap -share_map" option
2013-11-24 Clifford WolfEarly wire/reg/parameter width calculation in ast/simplify
2013-11-24 Clifford WolfUpdated TODOs
2013-11-24 Clifford WolfFixed xilinx/example_sim_counter test bench
2013-11-24 Clifford WolfAdded proper dumping of signed/unsigned parameters...
2013-11-24 Clifford WolfAdded support for signed parameters in ilang
2013-11-24 Clifford WolfRemoved now obsolete test cases
2013-11-24 Clifford WolfRemove auto_wire framework (smarter than the verilog...
2013-11-24 Clifford WolfImplemented correct handling of signed module parameters
2013-11-24 Clifford WolfAdded modelsim support to autotest
2013-11-24 Clifford WolfFixed "flatten" top-module detection: Only use on fully...
2013-11-24 Clifford WolfFixed "make install" dependencies
2013-11-24 Clifford WolfAdded "top" attribute to mark top module in hierarchy
2013-11-23 Clifford WolfUpdated command-reference-manual.tex
2013-11-23 Clifford WolfAppNote 010 typo fixes and corrections
2013-11-23 Clifford WolfAppNote 010 progress
2013-11-23 Clifford WolfImproved handling of techmap special wires
2013-11-23 Clifford WolfImproved handling of initialized registers
2013-11-23 Clifford WolfAdded more generic _TECHMAP_ wire mechanism to techmap...
2013-11-23 Clifford WolfMaking prograss on Appnote 010
2013-11-22 Clifford WolfProgress on AppNote 010
2013-11-22 Clifford WolfStarted to write on AppNote 010: Verilog to BLIF
2013-11-22 Clifford WolfUpdated command-reference-manual.tex
2013-11-22 Clifford WolfRenamed "placeholder" to "blackbox"
2013-11-22 Clifford WolfSome driver changes/fixes
2013-11-22 Clifford WolfFixed O(n^2) performance bug in verilog preprocessor
2013-11-22 Clifford WolfAdded more performance measurement infrastructure
2013-11-22 Clifford WolfEnable {* .. *} feature per default (removes dependency...
2013-11-22 Clifford WolfMassive performance improvement from refactoring RTLIL...
2013-11-22 Clifford WolfAdded SigBit struct and refactored RTLIL::SigSpec:...
2013-11-22 Clifford WolfImproved make rules for profiling and debugging
2013-11-21 Clifford WolfUpdated abc
2013-11-21 Clifford WolfImplemented $_DFFSR_ expression generator in verilog...
2013-11-21 Clifford WolfFixed async proc detection in mem2reg
2013-11-21 Clifford WolfMajor improvements in mem2reg and added "init" sync...
2013-11-21 Clifford WolfFixed a bug in "add -global_input"
2013-11-20 Clifford WolfAdded "proc_arst -global_arst" feature
2013-11-20 Clifford WolfFixed ilang parser: memory width
2013-11-20 Clifford WolfAdded "add" command (only wires for now)
2013-11-20 Clifford WolfAnother name resolution bugfix for generate blocks
2013-11-20 Clifford WolfImplemented indexed part selects
2013-11-20 Clifford WolfDo not allow memory bit select on the left side of...
2013-11-20 Clifford WolfAdded "synthesis" in (synopsys|synthesis) comment support
2013-11-20 Clifford WolfFixed name resolution of local tasks and functions...
2013-11-20 Clifford WolfImplemented part/bit select on memory read
2013-11-20 Clifford WolfUpdated TODOs in README file
2013-11-20 Clifford WolfAdded init= attribute for fpga-style reset values
2013-11-19 Clifford WolfAdded "make config-sudo"
2013-11-19 Clifford WolfInstall simlib in datdir
2013-11-19 Clifford WolfLarge improvements in yosys-config
2013-11-19 Clifford WolfFixed parsing of module arguments when one type is...
2013-11-19 Clifford WolfRenamed temp module generated by "abc" pass from "logic...
2013-11-18 Clifford WolfAdded additional mem2reg testcase
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