yosys.git
2016-03-31 Andrew ZonenbergMerge https://github.com/cliffordwolf/yosys
2016-03-31 Andrew ZonenbergUpdated tech lib for greenpak4 counter with some clarif...
2016-03-31 Andrew ZonenbergFixed typo in log message
2016-03-30 Clifford WolfWe have 2016 for a while now
2016-03-30 Clifford WolfAdded .vhd file extension support
2016-03-30 Andrew ZonenbergInitial work on greenpak4 counter extraction. Doesn...
2016-03-30 Clifford WolfMerge branch 'master' of github.com:cliffordwolf/yosys
2016-03-30 Clifford WolfAdded support for installed plugins
2016-03-30 Andrew ZonenbergAdded splitnets to synth_greenpak4
2016-03-29 Clifford WolfAdded more cell help messages
2016-03-29 Clifford WolfFixed indenting in techlibs/greenpak4/gp_dff.lib
2016-03-29 Clifford WolfMerge pull request #141 from azonenberg/master
2016-03-29 Andrew ZonenbergAdded keep constraint to GP_SYSRESET cell
2016-03-29 Andrew ZonenbergAdded GP_SYSRESET block
2016-03-28 Clifford WolfMerge pull request #137 from ravenexp/master
2016-03-28 Clifford WolfMerge pull request #138 from SebKuzminsky/help-typo
2016-03-28 Clifford WolfMerge pull request #139 from azonenberg/master
2016-03-27 Andrew ZonenbergAdded GP_COUNT8/GP_COUNT14 cells
2016-03-26 Andrew ZonenbergChanged GP_LFOSC parameter configuration
2016-03-26 Andrew ZonenbergAdded GP_LFOSC cell
2016-03-26 Andrew ZonenbergRenamed GP4_V* cells to GP_V* for consistency
2016-03-26 Sebastian Kuzminskyfix a cut-n-paste error in the -h help
2016-03-26 Sergey KvachonokEmbed DATDIR make variable value into yosys binary.
2016-03-25 Clifford WolfMerge pull request #136 from ravenexp/master
2016-03-25 Sergey KvachonokOptionally use ${CC} when compiling test utils.
2016-03-25 Sergey KvachonokAllow redefining pkg-config Makefile command.
2016-03-25 Sergey KvachonokAllow redefining binary and data install locations.
2016-03-24 Clifford WolfDo not set "nosync" on task outputs, fixes #134
2016-03-23 Clifford WolfFixed handling of inverters (aka 1-input luts) in nlutmap
2016-03-23 Clifford WolfAdded GP_DFFS, GP_DFFR, and GP_DFFSR
2016-03-23 Clifford WolfAdded GP_DFF INIT parameter
2016-03-22 Clifford WolfAdded ast.h to exported headers
2016-03-21 Clifford WolfCleanup abstract modules at end of "hierarchy -top"
2016-03-21 Clifford WolfSupport for abstract modules in chparam
2016-03-21 Clifford WolfAdded support for $stop system task
2016-03-21 Clifford WolfImprovements in synth_greenpak4, added -part option
2016-03-19 Clifford WolfImprovements in ABCEXTERNAL handling
2016-03-19 Clifford WolfMerge pull request #130 from ravenexp/master
2016-03-19 Sergey KvachonokSupport calling out to an external ABC.
2016-03-19 Clifford WolfAdded $display %m support, fixed mem leak in $display...
2016-03-19 Clifford WolfAdded black box modules for all the 7-series design...
2016-03-18 Clifford WolfFixed localparam signdness, fixes #127
2016-03-18 Clifford WolfSet "nosync" attribute on internal task/function wires
2016-03-15 Clifford WolfFixed Verilog parser fix and more similar improvements
2016-03-15 Andrew BeckerUse left-recursive rule for cell_port_list in Verilog...
2016-03-14 Clifford WolfBugfix in write_verilog for RTLIL processes
2016-03-11 Clifford WolfCleanups and improvements in examples/cmos/
2016-03-11 Clifford WolfMerge commit 'b34385ec924b6067c1f82bdbae923f8062518956'
2016-03-10 Clifford WolfFixed typos in verilog_defaults help message
2016-03-08 Clifford WolfAdded "write_edif -nogndvcc"
2016-03-08 Clifford WolfAdded examples/cxx-api/evaldemo.cc
2016-03-07 Clifford WolfMerge branch 'master' of github.com:cliffordwolf/yosys
2016-03-07 Clifford WolfUsing "mfs" and "lutpack" in ABC lut mapping
2016-03-05 Uros PlatiseCompleted ngspice digital example with verilog tb
2016-03-02 Clifford WolfAdded digital (xspice) example code to examples/cmos/
2016-03-02 Clifford WolfBe more conservative with net names in spice output
2016-02-29 Clifford WolfMerge pull request #119 from SebKuzminsky/spelling...
2016-02-28 Sebastian Kuzminskyuser-facing spelling fixes
2016-02-26 Clifford WolfWe are now in 0.6+ development
2016-02-26 Clifford WolfYosys 0.6 yosys-0.6
2016-02-24 Clifford WolfFixed BLIF parser for empty port assignments
2016-02-15 Clifford WolfUse easyer-to-read unoptimized ceil_log2()
2016-02-15 Clifford WolfUpdated ABC to ae7d65e71adc
2016-02-14 Clifford WolfUpdated command reference in manual
2016-02-14 Clifford WolfChangelog for upcoming 0.6 release
2016-02-14 Clifford WolfFixed more visual studio warnings
2016-02-13 Clifford WolfFixed some visual studio warnings
2016-02-13 Clifford WolfMerge branch 'master' of github.com:cliffordwolf/yosys
2016-02-13 Clifford WolfAdded "int ceil_log2(int)" function
2016-02-13 Clifford WolfFixed MXE ABC build
2016-02-13 Clifford WolfRun dffsr2dff in synth_xilinx
2016-02-13 Clifford WolfSupport for more Verific primitives (patch I got per...
2016-02-08 Clifford WolfUpdated ABC
2016-02-07 Clifford WolfWork around DDR dout sim glitches in ice40 SB_IO sim...
2016-02-07 Clifford WolfUpdated ABC
2016-02-04 Clifford WolfAdded "stat -liberty" for calculating chip area
2016-02-03 Clifford WolfBugfix in Verific front-end
2016-02-02 Clifford WolfUpdated verific build instructions
2016-02-02 Clifford WolfImproved dffsr2dff pass
2016-02-02 Clifford WolfAdded dffsr2dff
2016-02-02 Clifford WolfAdded addBufGate module method
2016-02-02 Clifford WolfUse alphanumerical order instead of idstring idx in...
2016-02-01 Clifford WolfAdded CodeOfConduct
2016-02-01 Clifford WolfUpdated ABC to hg rev ee212a9e94df
2016-02-01 Clifford WolfProgress in cell library documentation
2016-02-01 Clifford WolfAdded "abc -luts" option, Improved Xilinx logic mapping
2016-02-01 Clifford WolfImprovements in dfflibmap (FFs with Q/QN outputs, DFFs...
2016-02-01 Clifford WolfSigMap performance improvement
2016-02-01 Clifford Wolfhashlib mfp<> performance improvements
2016-01-31 Clifford WolfAdded reserve() method to haslib classes and
2016-01-31 Clifford WolfMerge branch 'rtlil_remove2_speedup' of https://github...
2016-01-31 Clifford WolfMore clang sanitizer stuff
2016-01-31 Rick Altherrrtlil: Improve performance of SigSpec::extract(SigSpec...
2016-01-31 Rick Altherrrtlil: speed up SigSpec::sort_and_unify()
2016-01-31 Rick Altherrrtlil: improve performance of SigSpec::replace(SigSpec...
2016-01-31 Rick Altherrgenrtlil: avoid converting SigSpec to set<SigBit> when...
2016-01-31 Rick Altherrrtlil: improve performance of SigSpec::remove2(SigSpec...
2016-01-31 Clifford WolfMeaningless coding style change
2016-01-31 Clifford WolfMerge branch 'rtlil_remove2_speedup' of https://github...
2016-01-31 Clifford WolfAddedd clang sanitizers
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