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yosys.git
2016-03-31
Andrew Zonenberg
Merge https://github.com/cliffordwolf/yosys
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2016-03-31
Andrew Zonenberg
Updated tech lib for greenpak4 counter with some clarif...
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2016-03-31
Andrew Zonenberg
Fixed typo in log message
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2016-03-30
Clifford Wolf
We have 2016 for a while now
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2016-03-30
Clifford Wolf
Added .vhd file extension support
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2016-03-30
Andrew Zonenberg
Initial work on greenpak4 counter extraction. Doesn...
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2016-03-30
Clifford Wolf
Merge branch 'master' of github.com:cliffordwolf/yosys
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2016-03-30
Clifford Wolf
Added support for installed plugins
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2016-03-30
Andrew Zonenberg
Added splitnets to synth_greenpak4
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2016-03-29
Clifford Wolf
Added more cell help messages
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2016-03-29
Clifford Wolf
Fixed indenting in techlibs/greenpak4/gp_dff.lib
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2016-03-29
Clifford Wolf
Merge pull request #141 from azonenberg/master
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2016-03-29
Andrew Zonenberg
Added keep constraint to GP_SYSRESET cell
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2016-03-29
Andrew Zonenberg
Added GP_SYSRESET block
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2016-03-28
Clifford Wolf
Merge pull request #137 from ravenexp/master
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2016-03-28
Clifford Wolf
Merge pull request #138 from SebKuzminsky/help-typo
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2016-03-28
Clifford Wolf
Merge pull request #139 from azonenberg/master
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2016-03-27
Andrew Zonenberg
Added GP_COUNT8/GP_COUNT14 cells
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2016-03-26
Andrew Zonenberg
Changed GP_LFOSC parameter configuration
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2016-03-26
Andrew Zonenberg
Added GP_LFOSC cell
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2016-03-26
Andrew Zonenberg
Renamed GP4_V* cells to GP_V* for consistency
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2016-03-26
Sebastian Kuzminsky
fix a cut-n-paste error in the -h help
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2016-03-26
Sergey Kvachonok
Embed DATDIR make variable value into yosys binary.
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2016-03-25
Clifford Wolf
Merge pull request #136 from ravenexp/master
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2016-03-25
Sergey Kvachonok
Optionally use ${CC} when compiling test utils.
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2016-03-25
Sergey Kvachonok
Allow redefining pkg-config Makefile command.
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2016-03-25
Sergey Kvachonok
Allow redefining binary and data install locations.
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2016-03-24
Clifford Wolf
Do not set "nosync" on task outputs, fixes #134
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2016-03-23
Clifford Wolf
Fixed handling of inverters (aka 1-input luts) in nlutmap
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2016-03-23
Clifford Wolf
Added GP_DFFS, GP_DFFR, and GP_DFFSR
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2016-03-23
Clifford Wolf
Added GP_DFF INIT parameter
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2016-03-22
Clifford Wolf
Added ast.h to exported headers
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2016-03-21
Clifford Wolf
Cleanup abstract modules at end of "hierarchy -top"
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2016-03-21
Clifford Wolf
Support for abstract modules in chparam
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2016-03-21
Clifford Wolf
Added support for $stop system task
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2016-03-21
Clifford Wolf
Improvements in synth_greenpak4, added -part option
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2016-03-19
Clifford Wolf
Improvements in ABCEXTERNAL handling
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2016-03-19
Clifford Wolf
Merge pull request #130 from ravenexp/master
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2016-03-19
Sergey Kvachonok
Support calling out to an external ABC.
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2016-03-19
Clifford Wolf
Added $display %m support, fixed mem leak in $display...
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2016-03-19
Clifford Wolf
Added black box modules for all the 7-series design...
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2016-03-18
Clifford Wolf
Fixed localparam signdness, fixes #127
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2016-03-18
Clifford Wolf
Set "nosync" attribute on internal task/function wires
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2016-03-15
Clifford Wolf
Fixed Verilog parser fix and more similar improvements
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2016-03-15
Andrew Becker
Use left-recursive rule for cell_port_list in Verilog...
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2016-03-14
Clifford Wolf
Bugfix in write_verilog for RTLIL processes
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2016-03-11
Clifford Wolf
Cleanups and improvements in examples/cmos/
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2016-03-11
Clifford Wolf
Merge commit 'b34385ec924b6067c1f82bdbae923f8062518956'
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2016-03-10
Clifford Wolf
Fixed typos in verilog_defaults help message
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2016-03-08
Clifford Wolf
Added "write_edif -nogndvcc"
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2016-03-08
Clifford Wolf
Added examples/cxx-api/evaldemo.cc
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2016-03-07
Clifford Wolf
Merge branch 'master' of github.com:cliffordwolf/yosys
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2016-03-07
Clifford Wolf
Using "mfs" and "lutpack" in ABC lut mapping
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2016-03-05
Uros Platise
Completed ngspice digital example with verilog tb
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2016-03-02
Clifford Wolf
Added digital (xspice) example code to examples/cmos/
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2016-03-02
Clifford Wolf
Be more conservative with net names in spice output
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2016-02-29
Clifford Wolf
Merge pull request #119 from SebKuzminsky/spelling...
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2016-02-28
Sebastian Kuzminsky
user-facing spelling fixes
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2016-02-26
Clifford Wolf
We are now in 0.6+ development
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2016-02-26
Clifford Wolf
Yosys 0.6
yosys-0.6
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2016-02-24
Clifford Wolf
Fixed BLIF parser for empty port assignments
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2016-02-15
Clifford Wolf
Use easyer-to-read unoptimized ceil_log2()
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2016-02-15
Clifford Wolf
Updated ABC to ae7d65e71adc
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2016-02-14
Clifford Wolf
Updated command reference in manual
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2016-02-14
Clifford Wolf
Changelog for upcoming 0.6 release
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2016-02-14
Clifford Wolf
Fixed more visual studio warnings
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2016-02-13
Clifford Wolf
Fixed some visual studio warnings
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2016-02-13
Clifford Wolf
Merge branch 'master' of github.com:cliffordwolf/yosys
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2016-02-13
Clifford Wolf
Added "int ceil_log2(int)" function
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2016-02-13
Clifford Wolf
Fixed MXE ABC build
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2016-02-13
Clifford Wolf
Run dffsr2dff in synth_xilinx
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2016-02-13
Clifford Wolf
Support for more Verific primitives (patch I got per...
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2016-02-08
Clifford Wolf
Updated ABC
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2016-02-07
Clifford Wolf
Work around DDR dout sim glitches in ice40 SB_IO sim...
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2016-02-07
Clifford Wolf
Updated ABC
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2016-02-04
Clifford Wolf
Added "stat -liberty" for calculating chip area
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2016-02-03
Clifford Wolf
Bugfix in Verific front-end
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2016-02-02
Clifford Wolf
Updated verific build instructions
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2016-02-02
Clifford Wolf
Improved dffsr2dff pass
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2016-02-02
Clifford Wolf
Added dffsr2dff
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2016-02-02
Clifford Wolf
Added addBufGate module method
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2016-02-02
Clifford Wolf
Use alphanumerical order instead of idstring idx in...
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2016-02-01
Clifford Wolf
Added CodeOfConduct
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2016-02-01
Clifford Wolf
Updated ABC to hg rev ee212a9e94df
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2016-02-01
Clifford Wolf
Progress in cell library documentation
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2016-02-01
Clifford Wolf
Added "abc -luts" option, Improved Xilinx logic mapping
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2016-02-01
Clifford Wolf
Improvements in dfflibmap (FFs with Q/QN outputs, DFFs...
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2016-02-01
Clifford Wolf
SigMap performance improvement
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2016-02-01
Clifford Wolf
hashlib mfp<> performance improvements
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2016-01-31
Clifford Wolf
Added reserve() method to haslib classes and
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2016-01-31
Clifford Wolf
Merge branch 'rtlil_remove2_speedup' of https://github...
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2016-01-31
Clifford Wolf
More clang sanitizer stuff
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2016-01-31
Rick Altherr
rtlil: Improve performance of SigSpec::extract(SigSpec...
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2016-01-31
Rick Altherr
rtlil: speed up SigSpec::sort_and_unify()
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2016-01-31
Rick Altherr
rtlil: improve performance of SigSpec::replace(SigSpec...
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2016-01-31
Rick Altherr
genrtlil: avoid converting SigSpec to set<SigBit> when...
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2016-01-31
Rick Altherr
rtlil: improve performance of SigSpec::remove2(SigSpec...
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2016-01-31
Clifford Wolf
Meaningless coding style change
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2016-01-31
Clifford Wolf
Merge branch 'rtlil_remove2_speedup' of https://github...
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2016-01-31
Clifford Wolf
Addedd clang sanitizers
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