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yosys.git
2019-06-06
Eddie Hung
Fix muxcover and its techmapping
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2019-06-06
Eddie Hung
Run muxpack and muxcover in synth_xilinx
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2019-06-06
Eddie Hung
Remove abc_flop attributes for now
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2019-06-06
Eddie Hung
Merge remote-tracking branch 'origin/eddie/muxpack...
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2019-06-06
Eddie Hung
Fix and test for balanced case
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2019-06-06
Eddie Hung
Merge remote-tracking branch 'origin/eddie/muxpack...
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2019-06-06
Eddie Hung
Fix warnings
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2019-06-06
Eddie Hung
Support cascading $pmux.A with $mux.A and $mux.B
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2019-06-06
Eddie Hung
More cleanup
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2019-06-06
Eddie Hung
Fix spacing
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2019-06-06
Eddie Hung
Non chain user check using next_sig
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2019-06-06
Eddie Hung
Add non exclusive test
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2019-06-06
Eddie Hung
Move muxpack from passes/techmap to passes/opt
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2019-06-06
Eddie Hung
Update doc
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2019-06-06
Eddie Hung
Add to CHANGELOG
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2019-06-06
Eddie Hung
One more and tidy up
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2019-06-06
Eddie Hung
Add a few more special case tests
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2019-06-06
Eddie Hung
Add tests, fix for !=
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2019-06-06
Eddie Hung
Missing file
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2019-06-06
Eddie Hung
Initial adaptation of muxpack from shregmap
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2019-06-06
Clifford Wolf
Merge pull request #1060 from antmicro/parsing_attr_on_...
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2019-06-06
David Shah
Merge pull request #1073 from whitequark/ecp5-diamond-iob
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2019-06-06
whitequark
ECP5: implement all Diamond I/O buffer primitives.
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2019-06-06
Clifford Wolf
Merge pull request #1071 from YosysHQ/eddie/fix_1070
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2019-06-06
Clifford Wolf
Merge pull request #1072 from YosysHQ/eddie/fix_1069
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2019-06-05
Eddie Hung
Missing doc for -tech xilinx in shregmap
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2019-06-05
Eddie Hung
Error out if no top module given before 'sim'
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2019-06-05
Eddie Hung
Fix typo in opt_rmdff
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2019-06-05
Eddie Hung
shregmap -tech xilinx_static to handle INIT
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2019-06-05
Eddie Hung
Continue support for ShregmapTechXilinx7Static
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2019-06-05
Eddie Hung
Update abc attributes on FD*E_1
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2019-06-05
Eddie Hung
Cleanup
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2019-06-05
Eddie Hung
Call shregmap -tech xilinx_static
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2019-06-05
Eddie Hung
Revert "Move ff_map back after ABC for shregmap"
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2019-06-05
Eddie Hung
Add -tech xilinx_static
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2019-06-05
Eddie Hung
Refactor to ShregmapTechXilinx7Static
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2019-06-05
Eddie Hung
shregmap -tech xilinx_dynamic to work -params and ...
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2019-06-05
Eddie Hung
Merge pull request #1067 from YosysHQ/clifford/fix1065
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2019-06-05
Eddie Hung
Merge remote-tracking branch 'origin/master' into xc7mux
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2019-06-05
Eddie Hung
Merge remote-tracking branch 'origin/clifford/fix1065...
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2019-06-05
Maciej Kurc
Fixed memory leak.
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2019-06-05
Clifford Wolf
Merge pull request #1066 from YosysHQ/clifford/fix1056
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2019-06-05
Clifford Wolf
Major rewrite of wire selection in setundef -init
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2019-06-05
Clifford Wolf
Indent fix
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2019-06-05
Clifford Wolf
Merge pull request #999 from jakobwenzel/setundefInitFix
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2019-06-05
Clifford Wolf
Fix typo in fmcombine log message, fixes #1063
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2019-06-05
Clifford Wolf
Suppress driver-driver conflict warning for unknown...
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2019-06-05
Clifford Wolf
Remove yosys_banner() from python wrapper init, fixes...
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2019-06-04
Eddie Hung
Rename shregmap -tech xilinx -> xilinx_dynamic
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2019-06-04
Eddie Hung
Add log_assert to ensure no loops
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2019-06-04
Eddie Hung
Only toposort builtin and abc types
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2019-06-04
Eddie Hung
Add space between -D and _ABC
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2019-06-04
Eddie Hung
Add (* abc_flop_q *) to brams_bb.v
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2019-06-04
Eddie Hung
Fix name clash
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2019-06-04
Eddie Hung
Add mux_map.v for wide mux
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2019-06-04
Clifford Wolf
Merge pull request #1062 from tux3/patch-1
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2019-06-04
Tux3
README.md: Missing formatting for <tag>
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2019-06-04
Maciej Kurc
Moved tests that fail with Icarus Verilog to /tests...
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2019-06-04
Eddie Hung
Move ff_map back after ABC for shregmap
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2019-06-04
Eddie Hung
Respect -nocarry
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2019-06-04
Eddie Hung
Fix pmux2shiftx logic
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2019-06-04
Eddie Hung
Merge mistake
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2019-06-04
Eddie Hung
Merge remote-tracking branch 'origin/master' into xc7mux
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2019-06-04
Eddie Hung
Merge pull request #1061 from YosysHQ/eddie/techmap_and...
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2019-06-04
Eddie Hung
Typo
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2019-06-04
Eddie Hung
Remove extra newline
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2019-06-04
Eddie Hung
IS_C_INVERTED
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2019-06-04
Eddie Hung
Execute techmap and arith_map simultaneously
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2019-06-03
Eddie Hung
Fix `ifndef
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2019-06-03
Eddie Hung
Make SB_LUT4 a whitebox, SB_DFF a blackbox (for now)
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2019-06-03
Eddie Hung
Assert that box_unique_id is indeed unique
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2019-06-03
Eddie Hung
Remove dupe
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2019-06-03
Eddie Hung
Skip internal modules when generating box_unique_id
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2019-06-03
Eddie Hung
When creating new holes cell, inherit parameters too
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2019-06-03
Eddie Hung
Ooopsie
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2019-06-03
Eddie Hung
Consistent with xilinx
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2019-06-03
Maciej Kurc
Added tests for attributes
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2019-06-02
Clifford Wolf
Only support Symbiotic EDA flavored Verific
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2019-06-01
Eddie Hung
Add flops as blackboxes
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2019-06-01
Eddie Hung
Add FD*E_1 -> FD*E techmap rules
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2019-06-01
Eddie Hung
Techmap flops before ABC again
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2019-06-01
Eddie Hung
parse_xaiger to cope with flops
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2019-05-31
Eddie Hung
ABC9 to understand flops
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2019-05-31
Eddie Hung
Merge branch 'xaig' into xc7mux
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2019-05-31
Eddie Hung
Throw out unused code inherited from abc
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2019-05-31
Maciej Kurc
Added support for parsing attributes on port connections.
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2019-05-31
Clifford Wolf
Fix "tee" handling of log_streams
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2019-05-30
Eddie Hung
Fix issue where keep signal became PI, but also box...
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2019-05-30
Eddie Hung
read_xaiger() to name box signals
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2019-05-30
Eddie Hung
Fix spelling
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2019-05-30
Eddie Hung
Remove whitebox attribute from DRAMs for now
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2019-05-30
Eddie Hung
Do not re-sort box_module ports
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2019-05-30
Eddie Hung
Remove whitespace
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2019-05-30
Eddie Hung
Revert "Re-enable &dc2"
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2019-05-30
Eddie Hung
Do not double count LUT1s
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2019-05-30
Eddie Hung
Carry in/out to be the last input/output for chains...
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2019-05-30
Clifford Wolf
Enable Verific flag veri_elaborate_top_level_modules_ha...
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2019-05-30
Clifford Wolf
Merge pull request #1057 from mmicko/fix_478
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2019-05-30
Eddie Hung
Re-enable &dc2
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2019-05-30
Eddie Hung
Reduce -W to 160
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