yosys.git
2014-09-22 Ahmed IrfanMerge branch 'master' of https://github.com/cliffordwol...
2014-09-21 Clifford WolfRe-enabled assert for new logic loops in "share" pass
2014-09-21 Clifford WolfVarious improvements regarding logic loops in "share...
2014-09-21 Clifford WolfLogic loop bugfix for "share" pass
2014-09-21 Clifford WolfAdded "share -limit"
2014-09-21 Clifford WolfStill loop bug in "share": changed assert to warning
2014-09-21 Clifford WolfDo not introduce new logic loops in "share"
2014-09-21 Clifford WolfAssert on new logic loops in "share" pass
2014-09-19 Clifford WolfAdded "test_abcloop" command
2014-09-19 Clifford WolfInitialize RTLIL::Const from std::vector<bool>
2014-09-19 Clifford WolfSorting of object names in ilang backend
2014-09-19 Clifford WolfSmall improvements in "abc" command handle_loops()...
2014-09-19 Clifford WolfUsing "NOT" instead of "INV" as cell name in default...
2014-09-19 Clifford WolfAlphabetically sort port names in "show" output
2014-09-18 Clifford WolfDo not run "scorr" in "abc -fast"
2014-09-18 Clifford WolfImprovements in "synth" script
2014-09-18 Clifford WolfAdded "abc -fast"
2014-09-18 ahmedirfan1983fixed memory next issue, when same memory is written...
2014-09-17 Clifford WolfAdded commit count to devel version number
2014-09-16 Clifford WolfFixed $_NOR vs. $_NOR_ typo in abc.cc
2014-09-16 Clifford WolfFixed $memwr/$memrd order in memory_dff
2014-09-16 Clifford WolfAdded new CodingReadme file (replaces CodingStyle and...
2014-09-16 Clifford WolfFixed $macc simlib model for zero-config
2014-09-15 Clifford WolfMore aggressive $macc merging in alumacc
2014-09-15 Clifford WolfAdded the obvious optimizations to alumacc $macc generator
2014-09-15 Clifford WolfImproved maccmap tree bit packing
2014-09-15 Clifford WolfFixed wreduce $shiftx handling
2014-09-14 Clifford WolfFixed monitor notifications for removed cell
2014-09-14 Clifford WolfAdded "synth" command
2014-09-14 Clifford WolfFixed techmap_wrap for techmap_celltype
2014-09-14 Clifford WolfUsing alumacc in techmap.v
2014-09-14 Clifford WolfVarious fixes/cleanups in alumacc and maccmap
2014-09-14 Clifford WolfAdded techmap_wrap attribute
2014-09-14 Clifford Wolfalumacc fix for $pos cells
2014-09-14 Clifford WolfExtract $alu cells in alumacc
2014-09-14 Clifford WolfMerge $macc cells in alumacc pass
2014-09-14 Clifford WolfBasic $macc extract in alumacc
2014-09-14 Clifford Wolfalumacc skeleton
2014-09-14 Clifford WolfCleanup in wreduce
2014-09-13 Clifford WolfUsing pkg-config to find libffi
2014-09-08 Clifford WolfFixed simlib $macc model for xilinx xsim
2014-09-08 Clifford WolfSimplified $fa undef model
2014-09-08 Clifford WolfFixes and cleanups for blackbox.v
2014-09-08 Clifford WolfAdded $lcu cell type
2014-09-08 Clifford WolfAnother $clog2 bugfix
2014-09-08 Clifford WolfAdded "$fa" cell type
2014-09-08 Clifford WolfTrim msb/lsb zero bits from full adder in maccmap
2014-09-08 Clifford WolfAdded "test_cell -const"
2014-09-07 Clifford WolfUsing maccmap for $macc and $mul techmap
2014-09-07 Clifford WolfAdded 'techmap_maccmap' techmap attribute
2014-09-07 Clifford WolfAdded "maccmap" command
2014-09-07 Clifford WolfAdded "test_cell -nosat"
2014-09-06 Clifford WolfVarious bug fixes (related to $macc model testing)
2014-09-06 Clifford WolfAdded $macc eval model
2014-09-06 Clifford WolfAdded $macc SAT model
2014-09-06 Clifford WolfFixed $clog2 (off by one error)
2014-09-06 Clifford WolfAdded $macc simlib model (also use as techmap rule...
2014-09-06 Clifford WolfFixed assignment of out-of bounds array element
2014-09-06 Clifford WolfAdded $macc cell type
2014-09-06 Clifford WolfFixed autotest for non-basename arguments
2014-09-06 Clifford WolfMerge branch 'master' of github.com:cliffordwolf/yosys
2014-09-06 Clifford WolfAdded "test_cell -script"
2014-09-06 Clifford WolfMerge pull request #38 from rubund/master
2014-09-06 Ruben UndheimCorrected spelling mistakes found by lintian
2014-09-04 Clifford WolfAdded tests/various/constmsk_test.ys
2014-09-04 Clifford WolfFixed "opt_const -fine" for $pos cells
2014-09-04 Clifford WolfRemoved $bu0 cell type
2014-09-03 Clifford WolfUsing $pos models for $bu0
2014-09-03 Clifford WolfFixed "test_cells -vlog"
2014-09-03 Clifford WolfFixes in $alu SAT- and eval-models
2014-09-02 Clifford WolfUndef-related fixes in simlib $alu model
2014-09-02 Clifford WolfImprovements in "test_cell -vlog"
2014-09-02 Clifford WolfAdded test_cell -vlog
2014-09-02 Clifford WolfCreate a default selection stack in RTLIL::Design:...
2014-09-02 Clifford WolfSmall bug fixes in $not, $neg, and $shiftx models
2014-09-02 Clifford WolfAdded SAT testing to test_cell eval stage
2014-09-02 Ahmed Irfanadded $pmux cell translation
2014-09-02 Clifford WolfRemoved references to yosys-svgviewer from docs
2014-09-02 Clifford WolfRemoved yosys-svgviewer
2014-09-02 Clifford WolfUsing "xdot" instead of "yosys-svgviewer" in show command
2014-09-01 Clifford WolfAdded $alu support to test_cell
2014-09-01 Clifford WolfAdded ConstEval model for $alu cells
2014-09-01 Clifford WolfAdded SAT model for $alu cells
2014-09-01 Clifford WolfFixed "test_cell -simlib all"
2014-09-01 Clifford WolfAdded "test_cell -simlib -v"
2014-09-01 Clifford WolfAdded "techmap -autoproc"
2014-09-01 Clifford WolfFixes in old SAT example.ys
2014-09-01 Clifford WolfMoved "share" and "wreduce" to passes/opt/
2014-09-01 Clifford WolfUsing std::vector<RTLIL::State> instead of RTLIL::Const...
2014-08-31 Clifford WolfAdded eval testing to test_cell
2014-08-31 Clifford WolfFixed return size of const_*() eval functions
2014-08-31 Clifford WolfAdded RTLIL::Const::size()
2014-08-31 Clifford WolfAdded eval model for $lut cells
2014-08-31 Clifford WolfTypo fixes in cell->*Param() API
2014-08-31 Clifford WolfAdded $lut support in test_cell, techmap, satgen
2014-08-30 Clifford WolfAdded design->scratchpad
2014-08-30 Clifford WolfAdded $alu cell type
2014-08-30 Clifford WolfAdded autotest -e (do not use -noexpr on write_verilog)
2014-08-30 Clifford WolfImproved write address decoder generation memory_map
2014-08-30 Clifford WolfFixed module->addPmux()
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