projects / nmigen.git / shortlog
? search:
summary | shortlog | log | commit | commitdiff | tree
first ⋅ prev ⋅ next
nmigen.git
2018-12-24 whitequarkback.rtlil: use one $meminit cell, not one per word. commit | commitdiff | tree
2018-12-24 whitequarkhdl.xfrm, back.rtlil: implement and use LHSGroupFilter. commit | commitdiff | tree
2018-12-24 whitequarkhdl.xfrm: implement SwitchCleaner, for pruning empty... commit | commitdiff | tree
2018-12-24 whitequarkback.rtlil: always output negative values as two's... commit | commitdiff | tree
2018-12-23 whitequarkback.rtlil: emit dummy logic to work around Verilog... commit | commitdiff | tree
2018-12-23 whitequarkback.rtlil: do not translate empty fragments. commit | commitdiff | tree
2018-12-23 whitequarkback.rtlil: only translate switch tests once. commit | commitdiff | tree
2018-12-23 whitequarkcli: generate: guess file type from extension. commit | commitdiff | tree
2018-12-23 whitequarkback.rtlil: fix swapped operands in mux codegen. commit | commitdiff | tree
2018-12-23 whitequarkcli: new module, for basic design generaton/simulation. commit | commitdiff | tree
2018-12-22 whitequarkhdl.xfrm: avoid cycles in union-find graph in LHSGroupA... commit | commitdiff | tree
2018-12-22 whitequarkcompat.genlib.fsm: fix naming for non-Signal LHS. commit | commitdiff | tree
2018-12-22 whitequarkhdl.ir: flatten hierarchy based on memory accesses... commit | commitdiff | tree
2018-12-22 whitequarkhdl.ir: factor out _merge_subfragment. NFC. commit | commitdiff | tree
2018-12-22 whitequarkback.rtlil: split processes as finely as possible. commit | commitdiff | tree
2018-12-22 whitequarkback.rtlil: remove useless condition. NFC. commit | commitdiff | tree
2018-12-22 whitequarkhdl.xfrm: implement LHSGroupAnalyzer. commit | commitdiff | tree
2018-12-22 whitequarkhdl.xfrm: Abstract*Transformer→*Visitor commit | commitdiff | tree
2018-12-22 whitequarkback.rtlil: always initialize the entire memory. commit | commitdiff | tree
2018-12-22 whitequarkcompat: use nicer names for next_value/next_value_ce... commit | commitdiff | tree
2018-12-22 whitequarkhdl.mem: allow changing init value after creating memory. commit | commitdiff | tree
2018-12-22 whitequarkback.verilog: do not rename internal signals. commit | commitdiff | tree
2018-12-22 whitequarkcompat: fix confusing naming for memory port address... commit | commitdiff | tree
2018-12-22 whitequarkhdl.ir: fix port propagation between siblings, in the... commit | commitdiff | tree
2018-12-22 whitequarkcompat: do not finalize native submodules twice. commit | commitdiff | tree
2018-12-21 whitequarkhdl.mem: use more informative signal naming for ports. commit | commitdiff | tree
2018-12-21 whitequarkhdl.ir: fix port propagation between siblings. commit | commitdiff | tree
2018-12-21 whitequarkcompat: provide verilog.convert shim. commit | commitdiff | tree
2018-12-21 whitequarkhdl.ir: do not flatten instances or collect ports from... commit | commitdiff | tree
2018-12-21 whitequarkcompat: provide Memory shim. commit | commitdiff | tree
2018-12-21 whitequarkhdl.mem: ensure transparent read port model has correct... commit | commitdiff | tree
2018-12-21 whitequarkback.pysim: handle out of bounds ArrayProxy indexes. commit | commitdiff | tree
2018-12-21 whitequarkback.pysim: give numeric names to unnamed subfragments... commit | commitdiff | tree
2018-12-21 whitequarkhdl.mem: use different naming for array signals. commit | commitdiff | tree
2018-12-21 whitequarkhdl.mem: add simulation model for memory. commit | commitdiff | tree
2018-12-21 whitequarkback.pysim: fix an issue with too few funclet slots. commit | commitdiff | tree
2018-12-21 whitequarkhdl.mem: add tests for all error conditions. commit | commitdiff | tree
2018-12-21 whitequarkhdl.mem: tie rdport.en high for asynchronous or transpa... commit | commitdiff | tree
2018-12-21 whitequarkback.rtlil: more consistent prefixing for subfragment... commit | commitdiff | tree
2018-12-21 whitequarkhdl.ir: correctly handle named output and inout ports. commit | commitdiff | tree
2018-12-21 whitequarkback.rtlil: implement memories. commit | commitdiff | tree
2018-12-21 whitequarkhdl.mem: implement memories. commit | commitdiff | tree
2018-12-21 whitequarkback.rtlil: explicitly pad constants with zeroes. commit | commitdiff | tree
2018-12-21 whitequarkback.rtlil: fix translation of Cat. commit | commitdiff | tree
2018-12-20 whitequarkir: allow non-Signals in Instance ports. commit | commitdiff | tree
2018-12-19 whitequarksetup: update pyvcd dependency, for var_type="string". commit | commitdiff | tree
2018-12-18 whitequarkcompat: import genlib.record from Migen. commit | commitdiff | tree
2018-12-18 whitequarkcompat: add wrappers for Slice.stop, Cat.l, _ArrayProxy... commit | commitdiff | tree
2018-12-18 whitequarkhdl.ast: Cat.{operands→parts} commit | commitdiff | tree
2018-12-18 whitequarkback.pysim: implement *. commit | commitdiff | tree
2018-12-18 whitequarktest.sim: add tests for sync functionality and errors. commit | commitdiff | tree
2018-12-18 whitequarkback.pysim: eliminate most dictionary lookups. commit | commitdiff | tree
2018-12-18 whitequarkhdl.ast, hdl.xfrm: various microoptimizations to speed... commit | commitdiff | tree
2018-12-18 whitequarkback.pysim: use arrays instead of dicts for signal... commit | commitdiff | tree
2018-12-18 whitequarkback.pysim: naming. NFC. commit | commitdiff | tree
2018-12-18 whitequarkback.pysim: fix an off-by-1 in add_sync_process(). commit | commitdiff | tree
2018-12-18 whitequarkback.pysim: trigger processes waiting on Tick() exactly... commit | commitdiff | tree
2018-12-18 whitequarkback.pysim: continue running simulator processes until... commit | commitdiff | tree
2018-12-18 whitequarkTravis: cache Yosys installation explicitly. commit | commitdiff | tree
2018-12-17 whitequarkfhdl.ir: add black-box fragments, fragment parameters... commit | commitdiff | tree
2018-12-17 whitequarkTravis: build and cache Yosys. commit | commitdiff | tree
2018-12-17 whitequarkhdl, back: add and use SignalSet/SignalDict. commit | commitdiff | tree
2018-12-17 whitequarkhdl.ast: factor out _MappedKeyDict, _MappedKeySet.... commit | commitdiff | tree
2018-12-17 whitequarkback.rtlil: update for Yosys master. commit | commitdiff | tree
2018-12-17 whitequarkback.rtlil: implement Array. commit | commitdiff | tree
2018-12-17 whitequarkback.rtlil: implement Part. commit | commitdiff | tree
2018-12-16 whitequarkback.rtlil: handle reset_less domains. commit | commitdiff | tree
2018-12-16 whitequarkhdl.dsl: add clock domain support. commit | commitdiff | tree
2018-12-16 whitequarkhdl.dsl: cleanup. NFC. commit | commitdiff | tree
2018-12-16 whitequarkback.rtlil: extract _StatementCompiler. NFC. commit | commitdiff | tree
2018-12-16 whitequarkback.rtlil: simplify. NFC. commit | commitdiff | tree
2018-12-16 whitequarkback.rtlil: properly escape strings in attributes. commit | commitdiff | tree
2018-12-16 whitequarkREADME: mention Yosys requirement. commit | commitdiff | tree
2018-12-16 whitequarkback.rtlil: prepare for Yosys sigspec slicing improvements. commit | commitdiff | tree
2018-12-16 whitequarkcompat.fhdl.structure: only convert to bool in If/Elif... commit | commitdiff | tree
2018-12-16 whitequarkback.rtlil: avoid illegal slices. commit | commitdiff | tree
2018-12-16 whitequarkback.rtlil: use slicing to match shape when reducing... commit | commitdiff | tree
2018-12-16 whitequarkback.rtlil: don't emit a slice if all bits are used. commit | commitdiff | tree
2018-12-16 whitequarkback.rtlil: reorganize value compiler into LHS/RHS. commit | commitdiff | tree
2018-12-16 whitequarkback.rtlil: fix naming. NFC. commit | commitdiff | tree
2018-12-16 whitequarkhdl.xfrm: separate AST traversal from AST identity... commit | commitdiff | tree
2018-12-16 whitequarkcompat.fhdl: reexport Array. commit | commitdiff | tree
2018-12-16 whitequarkback.pysim: implement LHS for Part, Slice, Cat, ArrayProxy. commit | commitdiff | tree
2018-12-15 whitequarktest.sim: generalize assertOperator. NFC. commit | commitdiff | tree
2018-12-15 whitequarkback.pysim: add (stub) LHSValueCompiler. commit | commitdiff | tree
2018-12-15 whitequarkback.pysim: implement Part. commit | commitdiff | tree
2018-12-15 whitequarkexamples: rename clkdiv/ctrl to ctr/ctr_ce. commit | commitdiff | tree
2018-12-15 whitequarkdoc: update COMPAT_SUMMARY. commit | commitdiff | tree
2018-12-15 whitequarkback.pysim: implement ArrayProxy. commit | commitdiff | tree
2018-12-15 whitequarkhdl.ast: implement Array and ArrayProxy. commit | commitdiff | tree
2018-12-15 whitequarkLower Python version requirement to 3.6. commit | commitdiff | tree
2018-12-15 whitequarkhdl: appropriately rename tests. NFC. commit | commitdiff | tree
2018-12-15 whitequarkhdl.ast: improve ClockSignal, ResetSignal documentation. commit | commitdiff | tree
2018-12-15 whitequarkRename fhdl→hdl, genlib→lib. commit | commitdiff | tree
2018-12-15 whitequarkMove star imports to make `from nmigen import *` usable. commit | commitdiff | tree
2018-12-15 whitequarkdoc: fix some Markdown awkwardness. commit | commitdiff | tree
2018-12-15 whitequarkdoc: update COMPAT_SUMMARY to reflect actual status. commit | commitdiff | tree
2018-12-15 whitequarkDetermine Migen's API surface and document compatibilit... commit | commitdiff | tree
2018-12-15 whitequarkpyback.sim: test Slice, Cat, Repl. commit | commitdiff | tree
2018-12-15 whitequarkfhdl.ast, back.pysim: implement shifts. commit | commitdiff | tree
next