yosys.git
2019-08-23 Eddie HungMerge remote-tracking branch 'origin/master' into xaig_...
2019-08-23 Eddie HungForgot one
2019-08-23 Eddie HungPut abc_* attributes above port
2019-08-23 Eddie HungMerge pull request #1326 from mmicko/doc-update
2019-08-23 Miodrag MilanovicMake macOS depenency clear
2019-08-22 Eddie HungDo not propagate mem2reg attribute through to result
2019-08-22 Eddie HungSpelling
2019-08-22 Eddie HungMerge pull request #1322 from mmicko/pyosys_osx
2019-08-22 Miodrag Milanovicdo not require boost if pyosys is not used
2019-08-22 Eddie HungMerge pull request #1319 from TeaEngineering/shuckc...
2019-08-22 Eddie HungMerge pull request #1317 from YosysHQ/eddie/opt_expr_shiftx
2019-08-22 Clifford WolfBump year in copyright notice
2019-08-22 Clifford WolfFix missing newline at end of file
2019-08-22 Clifford WolfMerge pull request #1289 from mmicko/anlogic_fixes
2019-08-22 Clifford WolfFix missing newline at end of file
2019-08-22 Clifford WolfMerge pull request #1281 from mmicko/efinix
2019-08-22 Eddie HungCopy-paste typo
2019-08-22 Chris Shucksmithrequire tcl-tk in Brewfile
2019-08-22 Eddie HungRespect opt_expr -keepdc as per @cliffordwolf
2019-08-22 Eddie HungHandle $shift and Y_WIDTH > 1 as per @cliffordwolf
2019-08-22 Eddie HungAdd cover()
2019-08-22 Eddie HungCanonical form
2019-08-22 Clifford WolfMerge pull request #1316 from YosysHQ/eddie/fix_mem2reg
2019-08-22 Eddie HungAdd test
2019-08-22 Eddie Hungopt_expr to trim A port of $shiftx if Y_WIDTH == 1
2019-08-21 whitequarkMerge pull request #1315 from mmicko/fix_dependencies
2019-08-21 Eddie Hungmem2reg to preserve user attributes and src
2019-08-21 Eddie HungUse semicolon
2019-08-21 Eddie Hungtechmap before read
2019-08-21 Eddie HungMerge remote-tracking branch 'origin/master' into xaig_...
2019-08-21 Eddie HungMerge remote-tracking branch 'origin/master' into xaig_...
2019-08-21 Eddie HungOutput "h" extension only if boxes
2019-08-21 Eddie HungRevert "Fix omode which inserts an output if none exist...
2019-08-21 Eddie HungAdd abc_arrival to SRL*
2019-08-21 Miodrag MilanovicFix test_pmgen deps
2019-08-21 Clifford WolfMerge pull request #1314 from YosysHQ/eddie/fix_techmap
2019-08-21 Eddie HungFix omode which inserts an output if none exists (other...
2019-08-21 Eddie HungRevert "Only xaig if GetSize(output_bits) > 0"
2019-08-21 Eddie HungOnly xaig if GetSize(output_bits) > 0
2019-08-21 Eddie HungMissing newline
2019-08-21 Eddie HungFix copy-paste typo
2019-08-21 Eddie HungOops
2019-08-21 Eddie HungMerge branch 'eddie/fix_techmap' into xaig_arrival
2019-08-21 Eddie HungGrammar
2019-08-21 Eddie HungAdd test
2019-08-21 Eddie Hungtechmap -max_iter to apply to each module individually
2019-08-21 Eddie Hungtechmap -max_iter to apply to each module individually
2019-08-21 Eddie Hungxilinx to use abc_map.v with -max_iter 1
2019-08-21 Eddie Hungecp5: remove DPR16X4 from abc_unmap.v
2019-08-21 Eddie Hungecp5 to use -max_iter 1
2019-08-21 Eddie Hungecp5 to use abc_map.v and _unmap.v
2019-08-21 Eddie HungAdd (* abc_arrival=<int> *) doc
2019-08-21 Eddie HungAdd reference to FD* timing
2019-08-21 Eddie HungRemove sequential extension
2019-08-21 Eddie HungRemove SRL* delays from cells_sim.v
2019-08-21 Eddie Hungretime_mode -> dff_mode
2019-08-21 Eddie HungLUTMUX -> LUTMUX6
2019-08-21 Eddie HungCleanup techmap in map_luts
2019-08-21 Eddie HungMove `techmap abc_map.v` into map_luts
2019-08-21 Eddie HungRemove delays from abc_map.v
2019-08-21 Eddie HungTypo
2019-08-21 Eddie HungMerge remote-tracking branch 'origin/master' into xaig_dff
2019-08-20 Eddie HungDo not sigmap!
2019-08-20 Eddie HungDeprecate `abc_scc_break` attribute
2019-08-20 Eddie HungWrap SRL{16,32} too
2019-08-20 Eddie HungWrap LUTRAMs in order to capture comb/seq behaviour
2019-08-20 Eddie HungMinor refactor
2019-08-20 Eddie HungAdd LUTRAM delays
2019-08-20 Eddie HungFix use of {CLK,EN}_POLARITY, also add a FIXME
2019-08-20 Eddie HungRemove mapping rules
2019-08-20 Eddie HungMerge pull request #1209 from YosysHQ/eddie/synth_xilinx
2019-08-20 Eddie HungRemove -icells
2019-08-20 Eddie HungUse abc_{map,unmap,model}.v
2019-08-20 Eddie HungMerge remote-tracking branch 'origin/master' into xaig_dff
2019-08-20 Eddie HungMerge pull request #1304 from YosysHQ/eddie/abc9_refactor
2019-08-20 Eddie HungMerge remote-tracking branch 'origin/master' into eddie...
2019-08-20 Clifford WolfMerge pull request #1298 from YosysHQ/clifford/pmgen
2019-08-20 Clifford WolfMerge branch 'master' into clifford/pmgen
2019-08-20 Clifford WolfAdd test case for real parameters
2019-08-20 Clifford WolfMerge pull request #1308 from jakobwenzel/real_params
2019-08-20 whitequarkMerge pull request #1309 from whitequark/proc_clean...
2019-08-19 Eddie HungMerge remote-tracking branch 'origin/master' into xaig_dff
2019-08-19 Eddie HungAdd arrival times for SRL outputs
2019-08-19 Eddie HungOutput i/o/h extensions even if no boxes or flops
2019-08-19 Eddie HungAdd BRAM arrival times
2019-08-19 Eddie HungRemove debug
2019-08-19 Eddie HungAdd reference to source of Tclktoq timing
2019-08-19 Eddie HungAdd (* abc_arrival *) attribute
2019-08-19 Eddie Hung Add 'abc_arrival' attribute for flop outputs
2019-08-19 Eddie HungUpdate box timings
2019-08-19 Eddie HungMove from cell attr to module attr
2019-08-19 Eddie HungFix typo
2019-08-19 Eddie HungFix typo
2019-08-19 Eddie HungID({A,B,Y}) -> ID::{A,B,Y} for opt_share.cc
2019-08-19 Eddie HungMerge remote-tracking branch 'origin/master' into xaig_dff
2019-08-19 Eddie HungClarify with 'only'
2019-08-19 Eddie HungUpdate doc
2019-08-19 Eddie HungUnify abc_carry_{in,out} into abc_carry and use port...
2019-08-19 Eddie HungUse attributes instead of params
2019-08-19 whitequarkproc_clean: fix order of switch insertion.
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