yosys.git
2019-08-30 Eddie HungMerge remote-tracking branch 'origin/master' into xaig_...
2019-08-30 Eddie HungMerge pull request #1321 from YosysHQ/eddie/xilinx_srl
2019-08-30 Eddie HungMerge branch 'eddie/xilinx_srl' into xaig_arrival
2019-08-30 Eddie HungMerge remote-tracking branch 'origin/master' into xaig_...
2019-08-30 Eddie HungFormat `-pwires`
2019-08-30 Eddie HungMerge remote-tracking branch 'origin/master' into eddie...
2019-08-30 David ShahMerge pull request #1343 from whitequark/diamond-ffs
2019-08-30 David Shahecp5: Add simulation equivalence check for Diamond...
2019-08-30 whitequarkecp5: deduplicate Diamond FD/IFS/OFS/IO primitives.
2019-08-30 whitequarkecp5: allow (and enable by default) GSR on FD/IFS/OFS...
2019-08-30 whitequarkecp5: add missing FD primitives.
2019-08-30 whitequarkecp5: fix CEMUX on IFS/OFS primitives.
2019-08-30 Eddie HungMerge pull request #1337 from YosysHQ/eddie/fix_carry_w...
2019-08-29 Eddie HungFix typo that's gone unnoticed for 5 months!?!
2019-08-29 Eddie HungRename boxes too
2019-08-29 Clifford WolfBump YOSYS_VER
2019-08-29 Eddie HungUse a dummy box file if none specified
2019-08-29 Eddie HungComment out SB_MAC16 arrival time for now, need to...
2019-08-29 Eddie HungAdd arrival for SB_MAC16.O
2019-08-29 Eddie HungAdd arrival times for U
2019-08-29 Eddie HungLX -> LP
2019-08-29 Eddie HungRound not floor
2019-08-29 Eddie HungAdd LP timings
2019-08-29 Eddie HungLX -> LP
2019-08-29 Eddie HungMerge remote-tracking branch 'origin/eddie/fix_carry_wr...
2019-08-29 Eddie HungAdd run-test.sh too
2019-08-29 Eddie HungDo not overwrite LUT param
2019-08-29 Eddie HungAdd SB_CARRY to ice40_opt test
2019-08-29 Eddie HungAdd ice40_opt test
2019-08-29 Eddie HungDo not overwrite LUT param
2019-08-29 Eddie HungAdd SB_CARRY to ice40_opt test
2019-08-29 Eddie HungAdd ice40_opt test
2019-08-29 Eddie HungCleanup
2019-08-29 Eddie HungRevert "Revert "Fix omode which inserts an output if...
2019-08-29 Eddie HungRevert "Output "h" extension only if boxes"
2019-08-29 Eddie HungMerge remote-tracking branch 'origin/eddie/fix_carry_wr...
2019-08-29 Eddie HungTrailing comma
2019-08-29 Eddie HungAdapt to $__ICE40_CARRY_WRAPPER
2019-08-29 Eddie HungRevert "Remove $__ICE40_FULL_ADDER handling from ice40_...
2019-08-29 Eddie HungAdd arrival times for HX devices
2019-08-29 Eddie HungSpecify ice40 family to cells_sim.v using define
2019-08-29 Eddie HungMerge remote-tracking branch 'origin/eddie/fix_carry_wr...
2019-08-29 Eddie HungRemove $__ICE40_FULL_ADDER handling from ice40_opt...
2019-08-29 Eddie HungUpdate box size and timings
2019-08-29 Eddie HungUpdate to new $__ICE40_CARRY_WRAPPER
2019-08-28 Eddie HungAccount for D port being a constant
2019-08-28 Eddie HungAccount for D port being a constant
2019-08-28 Eddie HungMerge branch 'eddie/xilinx_srl' into xaig_arrival
2019-08-28 Eddie HungMerge remote-tracking branch 'origin/master' into xaig_...
2019-08-28 Eddie HungMerge pull request #1334 from YosysHQ/clifford/async2sy...
2019-08-28 Eddie HungNo need to replace Q of slice since $shiftx is autoremove-d
2019-08-28 Eddie HungAdd (* clkbuf_sink *) to SRLC16E, reorder ports to...
2019-08-28 Eddie HungMore cleanup
2019-08-28 Eddie HungMore cleanup
2019-08-28 Eddie HungDo not use default_params dict, hardcode default values...
2019-08-28 Eddie HungAdd .gitignore
2019-08-28 Eddie HungUse test_pmgen for xilinx_srl
2019-08-28 Eddie HungAlways generate if no match
2019-08-28 Eddie HungRename test_pmgen arg xilinx_srl.{fixed,variable}
2019-08-28 Eddie HungDo not simplemap for variable test
2019-08-28 Eddie HungAdd xilinx_srl test
2019-08-28 Eddie HungMerge remote-tracking branch 'origin/master' into eddie...
2019-08-28 David ShahMerge pull request #1332 from YosysHQ/dave/ecp5gsr
2019-08-28 Clifford WolfMerge pull request #1335 from YosysHQ/clifford/paramap
2019-08-28 Clifford WolfFix typo
2019-08-28 Clifford WolfAdd "paramap" pass
2019-08-28 Clifford WolfAdd $dlatch support to async2sync
2019-08-27 Clifford WolfMerge pull request #1325 from YosysHQ/eddie/sat_init
2019-08-27 Marcin Kościelnickixilinx: Add SRLC16E primitive.
2019-08-27 Eddie HungMerge pull request #1292 from YosysHQ/mwk/xilinx_bufgmap
2019-08-27 Eddie HungIgnore all 1'bx in (* init *)
2019-08-27 Eddie HungRevert to using clean
2019-08-27 Marcin Kościelnickiimprove clkbuf_inhibit propagation upwards through...
2019-08-27 David Shahecp5: Add GSR support
2019-08-27 Clifford WolfAdd "make bumpversion"
2019-08-27 Eddie HungMissing close bracket
2019-08-27 Eddie HungRevert "In sat: 'x' in init attr should not override...
2019-08-27 Eddie HungRemove leftover header
2019-08-27 Eddie HungImprove xilinx_srl.fixed generate, add .variable generate
2019-08-27 Eddie HungAccount for maxsubcnt overflowing
2019-08-27 Eddie HungAdd xilinx_srl_pm.variable to test_pmgen
2019-08-26 Eddie HungPopulate generate for xilinx_srl.fixed pattern
2019-08-26 Eddie HungAdd xilinx_srl_fixed, fix typos
2019-08-26 Eddie HungMerge branch 'master' into eddie/xilinx_srl
2019-08-26 Eddie HungImprove tests to check that clkbuf is connected to...
2019-08-26 Eddie HungMerge branch 'master' into mwk/xilinx_bufgmap
2019-08-26 Eddie HungRemove dupe in CHANGELOG, missing end quote
2019-08-26 Clifford WolfMerge tag 'yosys-0.9'
2019-08-26 Clifford WolfYosys 0.9 yosys-0.9
2019-08-25 Clifford WolfMerge pull request #1112 from acw1251/pyosys_sigsig_issue
2019-08-24 Eddie HungWire with init on FF part, 1'bx on non-FF part
2019-08-24 Clifford WolfMerge pull request #1327 from YosysHQ/clifford/pmgen
2019-08-24 Eddie HungCreate new $__XILINX_SHREG_ cell for variable length too
2019-08-24 Eddie HungDo not allow Q of last cell of variable length SRL...
2019-08-24 Eddie HungAlso add first.Q to chain_bits since variable length
2019-08-24 Eddie HungDo not enforce !EN_POLARITY on $dffe
2019-08-24 Eddie HungCreate new cell for fixed length SRL
2019-08-24 Eddie HungCleanup FDRE matching
2019-08-23 Eddie HungAdd undocumented feature
2019-08-23 Eddie HungOops don't need a finally block
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