| 2019-09-13 | 
whitequark | lib.fifo: adjust properties to have consistent naming. | 
commit | commitdiff | tree | 
| 2019-09-12 | 
whitequark | build.plat: bypass tool detection if NMIGEN_*_env is...  | 
commit | commitdiff | tree | 
| 2019-09-12 | 
whitequark | vendor.xilinx_7series: Vivado requires bash on *nix...  | 
commit | commitdiff | tree | 
| 2019-09-12 | 
whitequark | hdl.mem: use keyword-only arguments as appropriate. | 
commit | commitdiff | tree | 
| 2019-09-12 | 
whitequark | lib.fifo: make fwft a keyword-only argument. | 
commit | commitdiff | tree | 
| 2019-09-12 | 
whitequark | lib.fifo: remove SyncFIFO.replace. | 
commit | commitdiff | tree | 
| 2019-09-12 | 
whitequark | README: update Yosys version requirement. | 
commit | commitdiff | tree | 
| 2019-09-12 | 
whitequark | lib.cdc: make domain properties private. | 
commit | commitdiff | tree | 
| 2019-09-12 | 
whitequark | lib.io: style. NFC. | 
commit | commitdiff | tree | 
| 2019-09-12 | 
whitequark | lib.cdc: adjust ResetSynchronizer for new CDC primitive...  | 
commit | commitdiff | tree | 
| 2019-09-12 | 
whitequark | lib.cdc: adjust MultiReg for new CDC primitive conventions. | 
commit | commitdiff | tree | 
| 2019-09-11 | 
whitequark | build.plat,vendor: allow clock constraints on arbitrary...  | 
commit | commitdiff | tree | 
| 2019-09-11 | 
whitequark | back: return name map from convert_fragment(). | 
commit | commitdiff | tree | 
| 2019-09-10 | 
whitequark | hdl.ast: warn if reset value is truncated. | 
commit | commitdiff | tree | 
| 2019-09-10 | 
Darrell Harmon | vendor.lattice_ecp5: pass ecppack_opts to ecppack. | 
commit | commitdiff | tree | 
| 2019-09-08 | 
whitequark | hdl.ast: check type of Sample(domain=...). | 
commit | commitdiff | tree | 
| 2019-09-08 | 
whitequark | hdl.dsl: add Default(), an alias for Case() with no...  | 
commit | commitdiff | tree | 
| 2019-09-08 | 
whitequark | hdl.mem,lib,examples: use Signal.range(). | 
commit | commitdiff | tree | 
| 2019-09-08 | 
whitequark | hdl.ast: add Signal.range(...), to replace Signal(min...  | 
commit | commitdiff | tree | 
| 2019-09-06 | 
whitequark | Remove nmigen.lib from prelude. | 
commit | commitdiff | tree | 
| 2019-09-06 | 
whitequark | Fix .gitignore. | 
commit | commitdiff | tree | 
| 2019-09-06 | 
whitequark | setup: replace versioneer with setuptools_scm. | 
commit | commitdiff | tree | 
| 2019-09-03 | 
whitequark | hdl.ast,back.rtlil: implement Cover. | 
commit | commitdiff | tree | 
| 2019-08-31 | 
whitequark | hdl.cd: add negedge clock domains. | 
commit | commitdiff | tree | 
| 2019-08-31 | 
Emily | _toolchain,build.plat,vendor.*: add required_tools...  | 
commit | commitdiff | tree | 
| 2019-08-30 | 
whitequark | vendor.lattice_ecp5: drive GSR synchronous to user...  | 
commit | commitdiff | tree | 
| 2019-08-30 | 
whitequark | build.dsl: allow both str and int resource attributes. | 
commit | commitdiff | tree | 
| 2019-08-28 | 
Emily | test.tools: use _toolchain.get_tool. | 
commit | commitdiff | tree | 
| 2019-08-28 | 
whitequark | _toolchain: new module, for injecting dependencies...  | 
commit | commitdiff | tree | 
| 2019-08-26 | 
whitequark | back.verilog: bump Yosys version requirement to 0.9. | 
commit | commitdiff | tree | 
| 2019-08-25 | 
whitequark | vendor.lattice_ecp5: revert default toolchain to Trellis. | 
commit | commitdiff | tree | 
| 2019-08-23 | 
whitequark | back.pysim: implement sim.add_clock(if_exists=True).  locally_working | 
commit | commitdiff | tree | 
| 2019-08-23 | 
whitequark | back.pysim: don't crash when trying to drive a nonexist...  | 
commit | commitdiff | tree | 
| 2019-08-23 | 
whitequark | build.run: add BuildPlan.digest(), useful for caching. | 
commit | commitdiff | tree | 
| 2019-08-22 | 
whitequark | vendor.lattice_ecp5: add Diamond support. | 
commit | commitdiff | tree | 
| 2019-08-22 | 
whitequark | vendor: eliminate unnecessary LUT instantiation. | 
commit | commitdiff | tree | 
| 2019-08-22 | 
Reto Kramer | examples/basic/uart: document `divisor` parameter. | 
commit | commitdiff | tree | 
| 2019-08-22 | 
whitequark | back.rtlil: print real parameters with maximum precision. | 
commit | commitdiff | tree | 
| 2019-08-22 | 
Darrell Harmon | back.rtlil: add support for real (float) parameters...  | 
commit | commitdiff | tree | 
| 2019-08-21 | 
Darrell Harmon | vendor.xilinx_series7: use STARTUPE2, not STARTUPE3. | 
commit | commitdiff | tree | 
| 2019-08-21 | 
whitequark | vendor.lattice_ice40: remove `--placer heap` default...  | 
commit | commitdiff | tree | 
| 2019-08-21 | 
whitequark | vendor: style. NFC. | 
commit | commitdiff | tree | 
| 2019-08-21 | 
whitequark | build.plat: remove TemplatedPlatform.unix_interpreter. | 
commit | commitdiff | tree | 
| 2019-08-21 | 
whitequark | back.pysim: allow coroutines as processes. | 
commit | commitdiff | tree | 
| 2019-08-20 | 
William D....  | test.test_examples: Convert pathlib-specific class...  | 
commit | commitdiff | tree | 
| 2019-08-19 | 
whitequark | back.verilog: parse output of `yosys -V`. | 
commit | commitdiff | tree | 
| 2019-08-19 | 
whitequark | Fix nmigen.__version__ to work on git-archive artifacts. | 
commit | commitdiff | tree | 
| 2019-08-19 | 
whitequark | build.plat, hdl.ir: coordinate missing domain creation. | 
commit | commitdiff | tree | 
| 2019-08-19 | 
whitequark | vendor.lattice_ice40: use a local clock domain in creat...  | 
commit | commitdiff | tree | 
| 2019-08-19 | 
whitequark | lib.cdc: use a local clock domain in ResetSynchronizer. | 
commit | commitdiff | tree | 
| 2019-08-19 | 
whitequark | README: fix typos. | 
commit | commitdiff | tree | 
| 2019-08-19 | 
whitequark | hdl.cd: implement local clock domains. | 
commit | commitdiff | tree | 
| 2019-08-19 | 
whitequark | back.pysim: index domains by identity, not by name. | 
commit | commitdiff | tree | 
| 2019-08-19 | 
whitequark | hdl.xfrm: lower resets in DomainLowerer as well. | 
commit | commitdiff | tree | 
| 2019-08-19 | 
whitequark | hdl.xfrm: consider fragment's own domains in DomainLowerer. | 
commit | commitdiff | tree | 
| 2019-08-19 | 
whitequark | formal→asserts | 
commit | commitdiff | tree | 
| 2019-08-19 | 
whitequark | tracer: fix typo. | 
commit | commitdiff | tree | 
| 2019-08-19 | 
whitequark | build.plat: do not prepare fragments twice. | 
commit | commitdiff | tree | 
| 2019-08-19 | 
whitequark | back.{rtlil,verilog}: split convert_fragment() off...  | 
commit | commitdiff | tree | 
| 2019-08-18 | 
Robin Heinemann | build.dsl: add conn argument to Connector. | 
commit | commitdiff | tree | 
| 2019-08-18 | 
whitequark | compat.fhdl.decorators: avoid using deprecated NativeCE...  | 
commit | commitdiff | tree | 
| 2019-08-18 | 
whitequark | hdl.xfrm: make deprecated CEInserter more well-behaved. | 
commit | commitdiff | tree | 
| 2019-08-15 | 
whitequark | hdl.ast: implement Initial. | 
commit | commitdiff | tree | 
| 2019-08-15 | 
whitequark | hdl.xfrm: sample cache should be per-fragment. | 
commit | commitdiff | tree | 
| 2019-08-12 | 
whitequark | hdl.xfrm: CEInserter→EnableInserter. | 
commit | commitdiff | tree | 
| 2019-08-08 | 
whitequark | hdl.ast: hash-cons ValueKey. | 
commit | commitdiff | tree | 
| 2019-08-08 | 
whitequark | tracer: use sys._getframe directly. | 
commit | commitdiff | tree | 
| 2019-08-08 | 
whitequark | compat.fhdl.decorators: port from oMigen. | 
commit | commitdiff | tree | 
| 2019-08-08 | 
whitequark | compat.fhdl.module: fix finalization of transformed...  | 
commit | commitdiff | tree | 
| 2019-08-07 | 
whitequark | vendor.lattice_ice40: add iCE5LP2K support. | 
commit | commitdiff | tree | 
| 2019-08-07 | 
whitequark | vendor.lattice_ice40: add iCE40UP3K support. | 
commit | commitdiff | tree | 
| 2019-08-07 | 
whitequark | vendor.lattice_ice40: add iCE5LP1K support. | 
commit | commitdiff | tree | 
| 2019-08-04 | 
whitequark | vendor.xilinx_{spartan_3_6,7series}: reconsider default...  | 
commit | commitdiff | tree | 
| 2019-08-04 | 
whitequark | vendor.xilinx_spartan_3_6: reconsider bitgen defaults. | 
commit | commitdiff | tree | 
| 2019-08-04 | 
whitequark | vendor.xilinx_spartan_3_6: set bitgen defaults to ...  | 
commit | commitdiff | tree | 
| 2019-08-04 | 
whitequark | vendor.xilinx_spartan_3_6: always use -w for map/par...  | 
commit | commitdiff | tree | 
| 2019-08-04 | 
whitequark | vendor.xilinx_spartan_3_6: do not use retiming by default. | 
commit | commitdiff | tree | 
| 2019-08-04 | 
whitequark | vendor.xilinx_spartan_3_6: force use of bash on UNIX. | 
commit | commitdiff | tree | 
| 2019-08-04 | 
whitequark | build.plat: allow selecting a specific UNIX shell inter...  | 
commit | commitdiff | tree | 
| 2019-08-04 | 
whitequark | vendor.lattice_ice40: avoid routing conflicts with...  | 
commit | commitdiff | tree | 
| 2019-08-04 | 
whitequark | back.rtlil: use a dummy wire, not 'x, when assigning...  | 
commit | commitdiff | tree | 
| 2019-08-03 | 
whitequark | back.rtlil: actually match shape of left hand side. | 
commit | commitdiff | tree | 
| 2019-08-03 | 
whitequark | vendor.lattice_ice40: add missing signal indexing. | 
commit | commitdiff | tree | 
| 2019-08-03 | 
whitequark | build.run: use keyword-only arguments where appropriate. | 
commit | commitdiff | tree | 
| 2019-08-03 | 
whitequark | compat.fhdl.specials: track changes in build.plat. | 
commit | commitdiff | tree | 
| 2019-08-03 | 
whitequark | hdl.dsl: reword m.If(~True) warning to be more clear. | 
commit | commitdiff | tree | 
| 2019-08-03 | 
whitequark | build.plat,vendor: automatically create sync domain...  | 
commit | commitdiff | tree | 
| 2019-08-03 | 
whitequark | hdl.ir: allow adding more than one domain in missing...  | 
commit | commitdiff | tree | 
| 2019-08-03 | 
whitequark | hdl.ir: don't expose as ports missing domains added...  | 
commit | commitdiff | tree | 
| 2019-08-03 | 
whitequark | build.plat: add default_rst, to be used with default_clk. | 
commit | commitdiff | tree | 
| 2019-08-03 | 
whitequark | build.plat: add default_clk{,_constraint,_frequency}. | 
commit | commitdiff | tree | 
| 2019-08-03 | 
whitequark | hdl.ir: allow returning elaboratables from missing...  | 
commit | commitdiff | tree | 
| 2019-08-03 | 
whitequark | hdl.ir: raise DomainError if a domain is used but not...  | 
commit | commitdiff | tree | 
| 2019-08-03 | 
whitequark | hdl.ir: call back from Fragment.prepare if a clock...  | 
commit | commitdiff | tree | 
| 2019-08-03 | 
whitequark | hdl.dsl: warn on suspicious statements like `m.If(...  | 
commit | commitdiff | tree | 
| 2019-08-03 | 
whitequark | Improve test added in 29fee01f to not leak warnings. | 
commit | commitdiff | tree | 
| 2019-08-03 | 
whitequark | back.rtlil: fix sim-synth mismatch with assigns followi...  | 
commit | commitdiff | tree | 
| 2019-08-03 | 
whitequark | hdl.ast: fix typo. | 
commit | commitdiff | tree | 
| 2019-08-03 | 
whitequark | hdl.ast: deprecate Value.part, add Value.{bit,word...  | 
commit | commitdiff | tree | 
| 2019-08-03 | 
whitequark | hdl.ast, back.rtlil: add source locations to anonymous...  | 
commit | commitdiff | tree | 
| next |