yosys.git
2014-03-06 Clifford WolfAdded freduce -stop
2014-03-06 Clifford WolfFixed gcc compiler warning
2014-03-06 Clifford WolfFixed undef handling in opt_reduce
2014-03-06 Clifford WolfFixes for improved techmap of shifts with large B inputs
2014-03-06 Clifford WolfFixed use of frozen literals in SatGen
2014-03-06 Clifford WolfStrictly zero-extend unsigned A-inputs of shift operati...
2014-03-06 Clifford WolfAdded techmap -max_iter option
2014-03-06 Clifford WolfImproved techmap of shift with wide B inputs
2014-03-06 Clifford WolfStrictly zero-extend unsigned A-inputs of shift operations
2014-03-05 Clifford WolfSwitched to EZMINISAT_SIMPSOLVER as default SAT solver
2014-03-05 Clifford WolfInclude id2ast pointers when dumping AST
2014-03-05 Clifford WolfFixed merging of compatible wire decls in AST frontend
2014-03-05 Clifford WolfBugfix in recursive AST simplification
2014-03-03 Clifford Wolffixed freduce for Minisat::SimpSolver: use frozen_literal()
2014-03-03 Clifford WolfezSAT: Added frozen_literal() API
2014-03-03 Clifford WolfezSAT: Fixed handling of eliminated Literals, added...
2014-03-01 Clifford WolfAdded ezSAT::eliminated API to help the SAT solver...
2014-03-01 Clifford WolfezSAT bugfix: don't call virtual methods in base class...
2014-03-01 Clifford WolfRemoved ezSAT::assumed() API
2014-03-01 Clifford WolfRemoved ezSAT built-in brute-froce solver
2014-03-01 Clifford WolfFixed vhdl2verilog temp dir name
2014-03-01 Clifford WolfFixed vhdl2verilog help message
2014-02-27 Clifford WolfFixed const folding of $bu0 cells
2014-02-26 Clifford WolfFixed bit-extending in $mux argument (use $bu0 instead...
2014-02-26 Clifford WolfAdded support for $bu0 to SatGen
2014-02-24 Clifford WolfDon't blow up constants unneccessarily in Verilog frontend
2014-02-23 Clifford WolfAdded support for Minisat::SimpSolver + ezSAT frezze...
2014-02-23 Clifford WolfFixed small memory leak in Pass::call()
2014-02-22 Clifford WolfFixed bug in generation of undefs for $memwr MUXes
2014-02-22 Clifford WolfFixed bug (typo) in passes/opt/opt_const.cc
2014-02-22 Clifford WolfAdded $lut support to blif backend (by user eddiehung...
2014-02-22 Clifford WolfAdded ezMiniSat EZMINISAT_INCREMENTAL compile-time...
2014-02-22 Clifford WolfMade MiniSat solver backend configurable in ezminisat.h
2014-02-21 Clifford WolfAdded workaround for vhdl-style edge triggers from...
2014-02-21 Clifford WolfAdded vhdl2verilog
2014-02-21 Clifford WolfProgress in presentation
2014-02-21 Clifford WolfBetter handling of nameDef and nameRef in edif backend
2014-02-21 Clifford WolfFixed instantiating multi-bit ports in edif backend
2014-02-21 Clifford WolfUse private namespace in mem_simple_4x1_map
2014-02-21 Clifford WolfAdded tests/techmap/mem_simple_4x1
2014-02-21 Clifford WolfRenamed "write_blif -subckt" to "write_blif -icells...
2014-02-21 Clifford WolfProgress in presentation
2014-02-20 Clifford WolfProgress in presentation
2014-02-20 Clifford WolfAdded _TECHMAP_REPLACE_ feature to techmap
2014-02-20 Clifford WolfAdded "extract -ignore_parameters" and "extract -ignore...
2014-02-20 Clifford WolfAdded "extract -map %<design_name>"
2014-02-20 Clifford WolfAdded "design -push" and "design -pop"
2014-02-20 Clifford WolfProgress in presentation
2014-02-20 Clifford WolfAdded connwrappers command
2014-02-20 Clifford WolfCleanups in handling of read_verilog -defer and -icells
2014-02-20 Clifford WolfProgress in presentation
2014-02-19 Clifford WolfAdded vcd2txt.pl and txt2tikztiming.py (tests/tools...
2014-02-18 Clifford WolfMerge branch 'master' of github.com:cliffordwolf/yosys
2014-02-18 Clifford WolfProgress in presentation
2014-02-18 Clifford WolfAdded techmap support for _TECHMAP_CONNMAP_*_
2014-02-18 Clifford WolfAdded "sat -dump_cnf"
2014-02-18 Clifford WolfCoding style corrections in SatHelper::dump_model_to_vcd()
2014-02-18 Clifford WolfImproved non-verbose ezSAT::printDIMACS() format
2014-02-18 Clifford WolfAdded "sat -initsteps"
2014-02-17 Clifford WolfAdded Verilog support for "`default_nettype none"
2014-02-17 Clifford WolfRenamed "sat -dump_fail_to_vcd" to "sat -dump_vcd"...
2014-02-17 Andrew ZonenbergAdded "-dump_fail_to_vcd" argument to SAT solver
2014-02-17 Clifford WolfProgress in presentation
2014-02-17 Clifford WolfBetter preserve wires when flattening (in comparison...
2014-02-16 Clifford WolfProgress in presentation
2014-02-16 Clifford WolfAdded some additional checks to techmap
2014-02-16 Clifford WolfAdded CONSTMSK and CONSTVAL feature to techmap
2014-02-16 Clifford WolfFixed handling of "keep" attribute on wires in opt_clean
2014-02-16 Clifford WolfAdded a warning note about error reporting to read_veri...
2014-02-16 Clifford WolfProgress in presentation
2014-02-16 Clifford WolfFixed use of selection in splitnets command
2014-02-16 Clifford WolfAdded recursion support to techmap
2014-02-16 Clifford WolfProgress in presentation
2014-02-16 Clifford WolfProgress in presentation
2014-02-16 Clifford WolfImproved support for constant functions
2014-02-15 Clifford WolfNow we are in Yoys 0.2.0+ development
2014-02-15 Clifford WolfTagging Yoys 0.2.0 yosys-0.2.0
2014-02-15 Clifford WolfAdded != support for relational select pattern
2014-02-15 Clifford WolfAdded iopadmap -bits
2014-02-15 Clifford WolfAdded ff and latch support to read_liberty
2014-02-15 Clifford WolfBugfix in expression parser of read_liberty
2014-02-15 Clifford WolfFixed dfflibmap for cell libraries with no set-reset-ff
2014-02-15 Clifford WolfCorrectly convert constants to RTLIL (fixed undef handling)
2014-02-15 Clifford WolfAdded frontend (-f) option to autotest.sh
2014-02-15 Clifford WolfFixed opt_const handling of double invert with non...
2014-02-15 Clifford WolfAdded liberty frontend
2014-02-14 Clifford WolfBe more conservative with new const-function code
2014-02-14 Clifford WolfAdded support for FOR loops in function calls in parameters
2014-02-14 Clifford WolfCreated basic support for function calls in parameter...
2014-02-14 Clifford WolfAdded abc -keepff option
2014-02-13 Clifford Wolfupdated default ABC command strings
2014-02-13 Clifford WolfUpdated ABC
2014-02-13 Clifford WolfImplemented read_verilog -defer
2014-02-13 Clifford WolfRemoved double blanks in ABC default command sequences
2014-02-13 Clifford WolfMerge branch 'master' of github.com:cliffordwolf/yosys
2014-02-13 Clifford WolfUpdated ABC and some related changes
2014-02-12 Clifford WolfMerge pull request #26 from ahmedirfan1983/btor
2014-02-12 Clifford WolfMerge branch 'master' of github.com:cliffordwolf/yosys
2014-02-12 Clifford WolfAdded support for functions returning integer
2014-02-12 Ahmed Irfanmodified btor synthesis script for correct use of splic...
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