2019-02-11 |
Gabe Black | systemc: scons: Specify RPATH as a list. |
commit | commitdiff | tree |
2019-02-08 |
Jairo Balart | cpu: Proposal for changing the indirect branch predicto... |
commit | commitdiff | tree |
2019-02-08 |
Tuan Ta | riscv: fix AMO, LR and SC instructions |
commit | commitdiff | tree |
2019-02-08 |
Tuan Ta | cpu: support atomic memory request type with AtomicOpFu... |
commit | commitdiff | tree |
2019-02-08 |
Moyang Wang | kern,sim: implement FUTEX_WAKE_OP |
commit | commitdiff | tree |
2019-02-08 |
Moyang Wang | sim, kern: support FUTEX_CMP_REQUEUE |
commit | commitdiff | tree |
2019-02-08 |
Tuan Ta | sim: handle the case when there're not enough HW thread... |
commit | commitdiff | tree |
2019-02-08 |
Tuan Ta | riscv: fixed syscall return value |
commit | commitdiff | tree |
2019-02-08 |
Tuan Ta | cpu: fix how branching is handled when a thread is... |
commit | commitdiff | tree |
2019-02-08 |
Tuan Ta | cpu: stop scheduling suspended threads in all stages... |
commit | commitdiff | tree |
2019-02-08 |
Tuan Ta | riscv: ignore nanosleep syscall |
commit | commitdiff | tree |
2019-02-08 |
Tuan Ta | sim,cpu: make exit_group halt all threads in a group |
commit | commitdiff | tree |
2019-02-08 |
Tuan Ta | arch-riscv: initialize RISC-V's thread pointer register... |
commit | commitdiff | tree |
2019-02-08 |
Tuan Ta | sim,kern: support FUTEX_WAIT_BITSET and FUTEX_WAKE_BITS... |
commit | commitdiff | tree |
2019-02-08 |
Tuan Ta | cpu: fixed how O3 CPU executes an exit system call |
commit | commitdiff | tree |
2019-02-08 |
Giacomo Travaglini | arch-arm: Fix Virtual interrupts in AArch64 |
commit | commitdiff | tree |
2019-02-08 |
Giacomo Travaglini | arch-arm: Fix extra comma in b7ce897f1e9545785bde982f72... |
commit | commitdiff | tree |
2019-02-08 |
Giacomo Travaglini | arch-arm: Allow ArmPPI usage for PMU |
commit | commitdiff | tree |
2019-02-08 |
Ruben Ayrapetyan | arch-arm: Fix initialization of PMU counters |
commit | commitdiff | tree |
2019-02-07 |
Giacomo Travaglini | configs, arch-arm: Using AddrRange for Realview mem_regions |
commit | commitdiff | tree |
2019-02-07 |
Giacomo Travaglini | configs: Unifiy interpretation of Realview mem_regions |
commit | commitdiff | tree |
2019-02-07 |
Austin Harris | arch-riscv: Enable support for riscv 32-bit in SE mode. |
commit | commitdiff | tree |
2019-02-06 |
Tuan Ta | riscv: remove NonSpeculative flag from fence inst |
commit | commitdiff | tree |
2019-02-06 |
Tuan Ta | cpu: fix how a thread starts up in MinorCPU |
commit | commitdiff | tree |
2019-02-06 |
Tuan Ta | arch-riscv: Initialize interrupt mask |
commit | commitdiff | tree |
2019-02-06 |
Ciro Santilli | scons: fix unused auto-generated blob variable in clang |
commit | commitdiff | tree |
2019-02-06 |
Andrea Mondelli | sim: added missed macro definition on MacOS |
commit | commitdiff | tree |
2019-02-05 |
Andrea Mondelli | misc: added missing override specifier |
commit | commitdiff | tree |
2019-02-05 |
Javier Bueno | cpu: Made the Loop Predictor a SimObject |
commit | commitdiff | tree |
2019-02-05 |
Jairo Balart | cpu: Made TAGE a SimObject that can be used by other... |
commit | commitdiff | tree |
2019-02-05 |
Austin Harris | riscv: Get rid of ISA specific register types in Interr... |
commit | commitdiff | tree |
2019-02-01 |
Javier Bueno | mem-cache: Updated version of the Signature Path Prefetcher |
commit | commitdiff | tree |
2019-02-01 |
Anouk Van Laer | dev, arm: Removed contextId variable |
commit | commitdiff | tree |
2019-02-01 |
Gabe Black | cpu, arch: Replace the CCReg type with RegVal. |
commit | commitdiff | tree |
2019-01-31 |
Andreas Sandberg | python: Remove getCode() type workaround |
commit | commitdiff | tree |
2019-01-31 |
Andreas Sandberg | sim: Prepare C++ side for Python 3 |
commit | commitdiff | tree |
2019-01-31 |
Andreas Sandberg | tests: Add a helper to run external scripts |
commit | commitdiff | tree |
2019-01-31 |
Andreas Sandberg | tests: Don't override tick rate in Ruby tests |
commit | commitdiff | tree |
2019-01-31 |
Gabe Black | power: Get rid of some ISA specific register types. |
commit | commitdiff | tree |
2019-01-31 |
Gabe Black | null: Get rid of some register type definitions. |
commit | commitdiff | tree |
2019-01-31 |
Gabe Black | mips: Stop using architecture specific register types. |
commit | commitdiff | tree |
2019-01-31 |
Gabe Black | alpha: Stop using architecture specific register types. |
commit | commitdiff | tree |
2019-01-31 |
Gabe Black | x86: Stop using/defining some ISA specific register... |
commit | commitdiff | tree |
2019-01-31 |
Gabe Black | riscv: Get rid of some ISA specific register types. |
commit | commitdiff | tree |
2019-01-31 |
Gabe Black | arch: cpu: Rename *FloatRegBits* to *FloatReg*. |
commit | commitdiff | tree |
2019-01-30 |
Giacomo Gabrielli | arch,cpu: Add vector predicate registers |
commit | commitdiff | tree |
2019-01-30 |
Giacomo Travaglini | configs: Enable DTB autogeneration in starter_fs.py |
commit | commitdiff | tree |
2019-01-30 |
Giacomo Travaglini | arch-arm, configs: Create single instance of DTB autoge... |
commit | commitdiff | tree |
2019-01-28 |
Ciro Santilli | tests: fix arm regression due to kernel not found |
commit | commitdiff | tree |
2019-01-25 |
Ciro Santilli | configs: fs.py remove --generate-dtb and enable it... |
commit | commitdiff | tree |
2019-01-25 |
Ciro Santilli | configs, arch-arm: don't search for default DTB and... |
commit | commitdiff | tree |
2019-01-25 |
Giacomo Travaglini | arch-arm: Remove floatReg operand type |
commit | commitdiff | tree |
2019-01-25 |
Giacomo Travaglini | arch-arm: Use VecElem instead of FloatReg for FP instru... |
commit | commitdiff | tree |
2019-01-25 |
Giacomo Travaglini | arch: Fix VecElem Operand generation in ISA parser |
commit | commitdiff | tree |
2019-01-25 |
Giacomo Travaglini | cpu, arch, arch-arm: Wire unused VecElem code in the... |
commit | commitdiff | tree |
2019-01-25 |
Giacomo Travaglini | cpu: O3 rename using the flatIndex instead of index |
commit | commitdiff | tree |
2019-01-25 |
Giacomo Travaglini | arch-arm: Inital vector rename mode depending on A32/A64 |
commit | commitdiff | tree |
2019-01-25 |
Giacomo Travaglini | cpu: Fix VecElemClass bugs in cpu models |
commit | commitdiff | tree |
2019-01-25 |
Giacomo Travaglini | cpu: Add VecElem entries in MinorCPU Scoreboard |
commit | commitdiff | tree |
2019-01-25 |
Giacomo Travaglini | arch-arm: Remove unused float operands |
commit | commitdiff | tree |
2019-01-25 |
Giacomo Travaglini | arch: Provide traceback when parsing ISA code |
commit | commitdiff | tree |
2019-01-25 |
Nicholas Lindsay | python: Always throw TypeError on slave-slave connections |
commit | commitdiff | tree |
2019-01-24 |
Gabe Black | hsail: Remove the MiscReg type. |
commit | commitdiff | tree |
2019-01-24 |
Gabe Black | base: arch: Get rid of the now unused FloatRegVal type. |
commit | commitdiff | tree |
2019-01-24 |
Ciro Santilli | dev-arm: fix --generate-dtb for ARM |
commit | commitdiff | tree |
2019-01-24 |
Rekai Gonzalez... | cpu-o3: O3 LSQ Generalisation |
commit | commitdiff | tree |
2019-01-23 |
Giacomo Travaglini | arch-arm: Implement LoadAcquire/StoreRelease in AArch32 |
commit | commitdiff | tree |
2019-01-23 |
Giacomo Travaglini | arch-arm: IsStoreConditional flag set depending on... |
commit | commitdiff | tree |
2019-01-23 |
Giacomo Travaglini | arch-arm: Remove SWP and SWPB instructions |
commit | commitdiff | tree |
2019-01-23 |
Gabe Black | systemc: Fix TLM related includes. |
commit | commitdiff | tree |
2019-01-23 |
Gabe Black | arm: Replace MiscReg with RegVal in utility.(hh|cc). |
commit | commitdiff | tree |
2019-01-23 |
Zicong Wang | mem-ruby: Fix missing TBE allocation and deallocation |
commit | commitdiff | tree |
2019-01-22 |
Gabe Black | sparc: Get rid of some register type definitions. |
commit | commitdiff | tree |
2019-01-22 |
Gabe Black | arch: cpu: Stop passing around misc registers by reference. |
commit | commitdiff | tree |
2019-01-22 |
Gabe Black | arm: Get rid of some register type definitions. |
commit | commitdiff | tree |
2019-01-22 |
Gabe Black | arm: dev: Replace ArmISA::MiscReg with RegVal in the... |
commit | commitdiff | tree |
2019-01-22 |
Ciro Santilli | arch-arm: implement the GDB XML target description... |
commit | commitdiff | tree |
2019-01-22 |
Ciro Santilli | ext: import GDB XML target description files for arm |
commit | commitdiff | tree |
2019-01-22 |
Ciro Santilli | scons: add helpers to access GDB XML description files |
commit | commitdiff | tree |
2019-01-22 |
Ciro Santilli | scons: allow embedding arbitrary blobs into the gem5... |
commit | commitdiff | tree |
2019-01-22 |
Ciro Santilli | base: add support for GDB's XML architecture definition |
commit | commitdiff | tree |
2019-01-22 |
Giacomo Travaglini | arch-arm: Move AArch32 IMPLEMENTATION DEFINED registers |
commit | commitdiff | tree |
2019-01-22 |
Sascha Bischoff | mem: Add tryTiming suppport to CommMonitor |
commit | commitdiff | tree |
2019-01-22 |
Brandon Potter | sim-se add readv and modifies writev |
commit | commitdiff | tree |
2019-01-22 |
Brandon Potter | sim-se: add ability to get/set sock metadata |
commit | commitdiff | tree |
2019-01-22 |
Brandon Potter | sim-se: add syscalls related to polling |
commit | commitdiff | tree |
2019-01-22 |
Brandon Potter | sim-se: add calls for network transmissions |
commit | commitdiff | tree |
2019-01-22 |
Brandon Potter | sim-se: add socket-based functionality |
commit | commitdiff | tree |
2019-01-18 |
Daniel R. Carvalho | base: Fix unitialized storage |
commit | commitdiff | tree |
2019-01-17 |
Gabe Black | tests: Fix tests/main.py so it can be run from anywhere. |
commit | commitdiff | tree |
2019-01-17 |
Nikos Nikoleris | mem: Allow inserts in the begining of a packet queue |
commit | commitdiff | tree |
2019-01-17 |
Nikos Nikoleris | mem: Determine if a packet queue forces ordering at... |
commit | commitdiff | tree |
2019-01-17 |
Nikos Nikoleris | cpu-o3: Make the smtCommitPolicy a Param.ScopedEnum |
commit | commitdiff | tree |
2019-01-17 |
Nikos Nikoleris | cpu-o3: Make the smtROBPolicy a Param.ScopedEnum |
commit | commitdiff | tree |
2019-01-17 |
Nikos Nikoleris | cpu-o3: Make the smtIQPolicy a Param.ScopedEnum |
commit | commitdiff | tree |
2019-01-17 |
Nikos Nikoleris | cpu-o3: Make the smtLSQPolicy a Param.ScopedEnum |
commit | commitdiff | tree |
2019-01-17 |
Nikos Nikoleris | cpu-o3: Make the smtFetchPolicy a Param.ScopedEnum |
commit | commitdiff | tree |
2019-01-17 |
Nikos Nikoleris | python: Add support for scoped enums |
commit | commitdiff | tree |
2019-01-16 |
Gabe Black | cpu: dev: sim: gpu-compute: Banish some ISA specific... |
commit | commitdiff | tree |
2019-01-16 |
Gabe Black | arch: Make the ISA register types aliases for the globa... |
commit | commitdiff | tree |
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