git.libre-soc.org Git - litex.git/shortlog

2011-12-11	Sebastien Bourdeauducq	bus: 14-bit CSR addresses	commit \| commitdiff \| tree
2011-12-11	Sebastien Bourdeauducq	bank: fix csrgen address decoder	commit \| commitdiff \| tree
2011-12-11	Sebastien Bourdeauducq	bus: Wishbone to CSR bridge	commit \| commitdiff \| tree
2011-12-11	Sebastien Bourdeauducq	corelogic: timeline module	commit \| commitdiff \| tree
2011-12-11	Sebastien Bourdeauducq	fhdl: remove broken fragment iadd	commit \| commitdiff \| tree
2011-12-11	Sebastien Bourdeauducq	convtools: insert reset on variables	commit \| commitdiff \| tree
2011-12-10	Sebastien Bourdeauducq	autofragment: remove debug	commit \| commitdiff \| tree
2011-12-10	Sebastien Bourdeauducq	fhdl: autofragment	commit \| commitdiff \| tree
2011-12-10	Sebastien Bourdeauducq	fhdl: fix += for empty fragment	commit \| commitdiff \| tree
2011-12-10	Sebastien Bourdeauducq	fhdl: pad support in fragments	commit \| commitdiff \| tree
2011-12-09	Sebastien Bourdeauducq	wishbone: decoder + shared bus interconnect	commit \| commitdiff \| tree
2011-12-09	Sebastien Bourdeauducq	fhdl: replication support	commit \| commitdiff \| tree
2011-12-08	Sebastien Bourdeauducq	wishbone: arbiter	commit \| commitdiff \| tree
2011-12-08	Sebastien Bourdeauducq	simplebus: export GetSigName function	commit \| commitdiff \| tree
2011-12-08	Sebastien Bourdeauducq	corelogic: multimux module	commit \| commitdiff \| tree
2011-12-08	Sebastien Bourdeauducq	verilog: handle default in case statements	commit \| commitdiff \| tree
2011-12-08	Sebastien Bourdeauducq	fhdl: improve automatic signal naming	commit \| commitdiff \| tree
2011-12-08	Sebastien Bourdeauducq	Corelogic conversion example	commit \| commitdiff \| tree
2011-12-08	Sebastien Bourdeauducq	corelogic: MC divider module	commit \| commitdiff \| tree
2011-12-08	Sebastien Bourdeauducq	fhdl: support negation operator	commit \| commitdiff \| tree
2011-12-08	Sebastien Bourdeauducq	verilog: fix unary operator conversion	commit \| commitdiff \| tree
2011-12-08	Sebastien Bourdeauducq	corelogic: round-robin module	commit \| commitdiff \| tree
2011-12-08	Sebastien Bourdeauducq	Named buses	commit \| commitdiff \| tree
2011-12-08	Sebastien Bourdeauducq	wishbone: add missing SEL	commit \| commitdiff \| tree
2011-12-08	Sebastien Bourdeauducq	instances: signal override	commit \| commitdiff \| tree
2011-12-08	Sebastien Bourdeauducq	Wishbone declarations	commit \| commitdiff \| tree
2011-12-08	Sebastien Bourdeauducq	Simple bus base class	commit \| commitdiff \| tree
2011-12-08	Sebastien Bourdeauducq	Instance support	commit \| commitdiff \| tree
2011-12-07	Sebastien Bourdeauducq	fhdl: fix implicit slice index	commit \| commitdiff \| tree
2011-12-07	Sebastien Bourdeauducq	fhdl: cleanup value bv	commit \| commitdiff \| tree
2011-12-05	Sebastien Bourdeauducq	Variable conversion	commit \| commitdiff \| tree
2011-12-05	Sebastien Bourdeauducq	Cleanup	commit \| commitdiff \| tree
2011-12-05	Sebastien Bourdeauducq	Case support + register bank generator	commit \| commitdiff \| tree
2011-12-04	Sebastien Bourdeauducq	CSR bus definitions	commit \| commitdiff \| tree
2011-12-04	Sebastien Bourdeauducq	Examples folder	commit \| commitdiff \| tree
2011-12-04	Sebastien Bourdeauducq	Reset insertion	commit \| commitdiff \| tree
2011-12-04	Sebastien Bourdeauducq	Verilog generator	commit \| commitdiff \| tree
2011-12-04	Sebastien Bourdeauducq	Initial import, FHDL basic structure, divider example	commit \| commitdiff \| tree

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