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yosys.git
2018-11-12
Clifford Wolf
Merge pull request #697 from eddiehung/xilinx_ps7
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2018-11-12
Clifford Wolf
Merge pull request #695 from daveshah1/ecp5_bb
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2018-11-10
Eddie Hung
Add support for Xilinx PS7 block
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2018-11-09
Clifford Wolf
Set Verific flag vhdl_support_variable_slice=1
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2018-11-09
David Shah
ecp5: Add 'fake' DCU parameters
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2018-11-09
David Shah
ecp5: Add blackboxes for ancillary DCU cells
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2018-11-09
Clifford Wolf
Merge pull request #696 from arjenroodselaar/verific_darwin
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2018-11-08
Clifford Wolf
Fix "make ystests" to use correct Yosys binary
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2018-11-08
Arjen Roodselaar
Use appropriate static libraries when building with...
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2018-11-07
Clifford Wolf
Merge pull request #693 from YosysHQ/rlimit
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2018-11-07
David Shah
ecp5: Adding some blackbox cells
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2018-11-07
Clifford Wolf
Limit stack size to 16 MB on Darwin
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2018-11-06
Clifford Wolf
Merge pull request #694 from trcwm/dffmap_expr_fix
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2018-11-06
Niels Moseley
DFFLIBMAP: changed 'missing pin' error into a warning...
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2018-11-06
Clifford Wolf
Run solver in non-incremental mode whem smtio.py is...
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2018-11-06
Clifford Wolf
Update ABC rev to 4d56acf
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2018-11-06
Clifford Wolf
Fix for improved smtio.py rlimit code
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2018-11-06
Clifford Wolf
Improve stack rlimit code in smtio.py
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2018-11-05
Clifford Wolf
Allow square brackets in liberty identifiers
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2018-11-05
Clifford Wolf
Merge pull request #691 from arjenroodselaar/stacksize
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2018-11-05
Arjen Roodselaar
Use conservative stack size for SMT2 on MacOS
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2018-11-04
Clifford Wolf
Add warning for SV "restrict" without "property"
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2018-11-04
Clifford Wolf
Add proper error message for when smtbmc "append" fails
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2018-11-04
Clifford Wolf
Various indenting fixes in AST front-end (mostly space...
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2018-11-04
Clifford Wolf
Merge pull request #687 from trcwm/master
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2018-11-04
Clifford Wolf
Merge pull request #688 from ZipCPU/rosenfell
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2018-11-03
ZipCPU
Make and dependent upon LSB only
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2018-11-03
Niels Moseley
Liberty file newline handling is more relaxed. More...
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2018-11-03
Niels Moseley
Report an error when a liberty file contains pin refere...
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2018-11-01
Clifford Wolf
Do not generate "reg assigned in a continuous assignmen...
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2018-11-01
Clifford Wolf
Add support for signed $shift/$shiftx in smt2 back-end
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2018-10-31
Clifford Wolf
Merge branch 'igloo2'
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2018-10-31
Clifford Wolf
Fix sf2 LUT interface
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2018-10-31
Clifford Wolf
Basic SmartFusion2 and IGLOO2 synthesis support
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2018-10-30
Clifford Wolf
Merge pull request #680 from jburgess777/fix-empty...
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2018-10-28
Jon Burgess
Avoid assert when label is an empty string
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2018-10-25
Clifford Wolf
Merge pull request #678 from whentze/master
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2018-10-25
Clifford Wolf
Fix minor typo in error message
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2018-10-25
Clifford Wolf
Merge pull request #679 from udif/pr_syntax_error
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2018-10-24
Udi Finkelstein
Rename the generic "Syntax error" message from the...
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2018-10-23
Clifford Wolf
Merge pull request #677 from daveshah1/ecp5_dsp
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2018-10-22
whentze
fix unhandled std::out_of_range when calling yosys...
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2018-10-22
David Shah
ecp5: Remove DSP parameters that don't work
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2018-10-21
David Shah
ecp5: Add DSP blackboxes
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2018-10-20
Clifford Wolf
Improve read_verilog range out of bounds warning
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2018-10-20
Clifford Wolf
Merge pull request #674 from rubund/feature/svinterface...
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2018-10-20
Ruben Undheim
Refactor code to avoid code duplication + added comments
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2018-10-20
Ruben Undheim
Support for SystemVerilog interfaces as a port in the...
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2018-10-20
Ruben Undheim
Fixed memory leak
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2018-10-19
Clifford Wolf
Merge pull request #673 from daveshah1/ecp5_improve
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2018-10-19
David Shah
ecp5: Sim model fixes
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2018-10-19
David Shah
ecp5: Add latch inference
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2018-10-19
Clifford Wolf
Merge pull request #672 from daveshah1/fix_bram
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2018-10-19
David Shah
memory_bram: Reset make_outreg when growing read ports
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2018-10-19
Clifford Wolf
Merge pull request #671 from rafaeltp/master
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2018-10-19
Clifford Wolf
Merge pull request #670 from rubund/feature/basic_svint...
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2018-10-18
rafaeltp
adding offset info to memories
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2018-10-18
rafaeltp
adding offset info to memories
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2018-10-18
Ruben Undheim
Basic test for checking correct synthesis of SystemVeri...
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2018-10-18
Clifford Wolf
Update ABC to git rev 14d985a
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2018-10-18
Clifford Wolf
Merge pull request #659 from rubund/sv_interfaces
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2018-10-18
Clifford Wolf
Merge pull request #657 from mithro/xilinx-vpr
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2018-10-18
Clifford Wolf
Merge pull request #664 from tklam/ignore-verilog-protect
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2018-10-17
Clifford Wolf
Update ABC to git rev c5b48bb
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2018-10-17
Clifford Wolf
Minor code cleanups in liberty front-end
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2018-10-17
Clifford Wolf
Merge pull request #660 from tklam/parse-liberty-detect...
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2018-10-17
Clifford Wolf
Merge pull request #663 from aman-goel/master
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2018-10-17
Clifford Wolf
Merge pull request #658 from daveshah1/ecp5_bram
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2018-10-17
Clifford Wolf
Merge pull request #641 from tklam/master
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2018-10-17
Clifford Wolf
Merge pull request #638 from udif/pr_reg_wire_error
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2018-10-16
Clifford Wolf
We have 2018 now
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2018-10-16
Clifford Wolf
After release is before release
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2018-10-16
Clifford Wolf
Merge branch 'yosys-0.8-rc'
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2018-10-16
Clifford Wolf
Yosys 0.8
yosys-0.8
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2018-10-16
argama
ignore protect endprotect
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2018-10-16
Clifford Wolf
Update command reference manual
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2018-10-16
David Shah
ecp5: Disable LSR inversion
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2018-10-15
Aman Goel
Minor update
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2018-10-13
Ruben Undheim
Handle FIXME for modport members without type directly...
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2018-10-13
Ruben Undheim
Documentation improvements etc.
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2018-10-13
argama
detect ff/latch before processing other nodes
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2018-10-13
tklam
stop check_signal_in_fanout from traversing FFs
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2018-10-13
tklam
stop check_signal_in_fanout from traversing FFs
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2018-10-13
tklam
Merge branch 'master' of https://github.com/YosysHQ...
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2018-10-12
Ruben Undheim
Fix build error with clang
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2018-10-12
Ruben Undheim
Support for 'modports' for System Verilog interfaces
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2018-10-12
Ruben Undheim
Synthesis support for SystemVerilog interfaces
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2018-10-12
David Shah
BRAM improvements
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2018-10-10
David Shah
ecp5: Adding BRAM maps for all size options
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2018-10-10
David Shah
ecp5: First BRAM type maps successfully
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2018-10-10
David Shah
ecp5: Script for BRAM IO connections
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2018-10-09
David Shah
ecp5: Adding BRAM initialisation and config
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2018-10-08
Tim 'mithro...
xilinx: Still map LUT7/LUT8 to Xilinx specific primitives.
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2018-10-07
Clifford Wolf
Improve Verific importer blackbox handling
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2018-10-05
David Shah
ecp5: Add blackbox for DP16KD
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2018-10-05
Clifford Wolf
Merge pull request #651 from ARandomOWL/stdcells_fix
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2018-10-05
Clifford Wolf
Add "write_edif -attrprop"
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2018-10-05
Clifford Wolf
Merge pull request #654 from mithro/patch-1
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2018-10-05
Clifford Wolf
Fix compiler warning in verific.cc
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2018-10-05
Tim Ansell
Fix misspelling in issue_template.md
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