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yosys.git
2022-05-26
Aki Van Ness
pass jny: fixed the signed output for param value output
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2022-05-26
Aki Van Ness
pass jny: added connection output
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2022-05-26
Aki Van Ness
pass jny: added filter options for including connection...
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2022-05-26
Aki Van Ness
pass jny: large chunk of refactoring to make the JSON...
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2022-05-26
Aki Van Ness
metadata -> jny: migrated to the proper name for the...
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2022-05-26
Aki Van Ness
pass metadata: added the machinery to write param and...
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2022-05-26
Aki Van Ness
pass metadata: removed superfluous `stringf` calls
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2022-05-26
Aki Van Ness
pass metadata: some more rough work on dumping the...
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2022-05-26
Aki Van Ness
pass metadata: fixed the MetadataWriter object initiali...
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2022-05-26
Aki Van Ness
pass metadata: added the output of parameters,
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2022-05-26
Aki Van Ness
pass metadata: fixed some of the output formatting
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2022-05-26
Aki Van Ness
pass metadata: initial commit of the metadata pass...
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2022-05-26
Marcelina Kościelnicka
ecp5: Do not use specify in generate in cells_sim.v.
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2022-01-11
Miodrag Milanovic
Release version 0.13
yosys-0.13
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2022-01-11
Miodrag Milanovic
Update CHANGELOG
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2022-01-09
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2022-01-08
Zachary Snow
sv: auto add nosync to certain always_comb local vars
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2022-01-08
Zachary Snow
sv: fix size cast internal expression extension
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2022-01-05
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2022-01-04
Zachary Snow
logger: fix unmatched expected warnings and errors
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2022-01-04
Austin Seipp
opt_dff: fix sequence point copy paste bug
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2022-01-04
gatecat
manual: Fix cell-stmt order
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2022-01-04
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2022-01-03
Zachary Snow
fix iverilog compatibility for new case expr tests
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2022-01-03
Zachary Snow
fixup verilog doubleslash test
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2022-01-03
Zachary Snow
sv: fix size cast clipping expression width
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2022-01-03
Miodrag Milanovic
Update manual
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2021-12-26
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2021-12-25
Catherine
Merge pull request #3127 from whitequark/cxxrtl-no...
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2021-12-25
Catherine
cxxrtl: don't reset elided wires with \init attribute.
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2021-12-22
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2021-12-21
Lofty
intel_alm: disable 256x40 M10K mode
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2021-12-21
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2021-12-20
Marcelina Kościelnicka
memory_share: Fix SAT-based sharing for wide ports.
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2021-12-19
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2021-12-18
Zachary Snow
fix width detection of array querying function in case...
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2021-12-17
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2021-12-16
Catherine
Merge pull request #3115 from whitequark/issue-3112
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2021-12-16
Catherine
Merge pull request #3114 from whitequark/issue-3113
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2021-12-16
Thomas Sailer
preprocessor: do not destroy double slash escaped ident...
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2021-12-15
Catherine
cxxrtl: demote wires not inlinable only in debug_eval...
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2021-12-15
Catherine
bugpoint: avoid infinite loop between -connections...
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2021-12-15
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2021-12-14
Catherine
Merge pull request #3111 from whitequark/issue-3110
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2021-12-14
Claire Xenia...
Hotfix for run_shell auto-detection
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2021-12-14
Catherine
Fix null pointer dereference after failing to extract...
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2021-12-14
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2021-12-13
Claire Xen
Merge pull request #3108 from YosysHQ/claire/verificdefs
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2021-12-13
Claire Xenia...
Add YOSYS to the implicitly defined verilog macros...
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2021-12-13
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2021-12-12
Marcelina Kościelnicka
Add clean_zerowidth pass, use it for Verilog output.
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2021-12-12
Catherine
Merge pull request #3105 from whitequark/cxxrtl-reset...
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2021-12-12
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2021-12-12
Marcelina Kościelnicka
Fix unused param warning with ENABLE_NDEBUG.
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2021-12-12
Marcelina Kościelnicka
rtlil: Dump empty connections when whole module is...
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2021-12-11
Catherine
cxxrtl: preserve interior memory pointers across reset.
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2021-12-11
Catherine
Merge pull request #3103 from whitequark/write_verilog...
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2021-12-11
whitequark
cxxrtl: use unique_ptr<value<>[]> to store memory contents.
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2021-12-11
whitequark
write_verilog: dump zero width sigspecs correctly.
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2021-12-11
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2021-12-10
Miodrag Milanović
Merge pull request #3102 from YosysHQ/claire/enumxz
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2021-12-10
Claire Xenia...
Fix verific import of enum values with x and/or z
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2021-12-10
Miodrag Milanović
Merge pull request #3097 from YosysHQ/modport
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2021-12-10
Claire Xen
Update verific.cc
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2021-12-10
Claire Xen
Merge pull request #3099 from YosysHQ/claire/readargs
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2021-12-09
Claire Xenia...
Fix the tests we just broke
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2021-12-09
Claire Xenia...
Added "yosys -r <topmodule>"
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2021-12-09
Claire Xenia...
Use "read" command to parse HDL files from Yosys comman...
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2021-12-09
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2021-12-08
Marcelina Kościelnicka
opt_mem_priority: Fix non-ascii char in help message.
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2021-12-08
Miodrag Milanovic
If direction NONE use that from first bit
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2021-12-04
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2021-12-03
Miodrag Milanovic
Next dev cycle
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2021-12-03
Miodrag Milanovic
Release version 0.12
yosys-0.12
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2021-12-03
Miodrag Milanovic
Update manual
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2021-12-03
Miodrag Milanovic
Add gitignore for gatemate
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2021-12-03
Miodrag Milanovic
Make sure cell names are unique for wide operators
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2021-12-02
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2021-12-01
Miodrag Milanovic
Update CHANGELOG and CODEOWNERS
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2021-11-26
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2021-11-25
Lofty
intel_alm: preliminary Arria V support
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2021-11-25
Lofty
sta: very crude static timing analysis pass
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2021-11-18
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2021-11-17
Miodrag Milanović
Merge pull request #3080 from YosysHQ/micko/init_wire
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2021-11-17
Miodrag Milanovic
Give initial wire unique ID, fixes #2914
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2021-11-17
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2021-11-16
Kamil Rakoczy
Support parameters using struct as a wiretype (#3050)
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2021-11-14
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2021-11-13
Patrick Urban
synth_gatemate Revert cascade A/B port mixup
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2021-11-13
Patrick Urban
synth_gatemate: Remove iob_map invokation
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2021-11-13
Patrick Urban
synth_gatemate: Add block RAM cascade support
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2021-11-13
Patrick Urban
synth_gatemate: Remove obsolete iob_map
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2021-11-13
Patrick Urban
synth_gatemate: Update pass
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2021-11-13
Patrick Urban
synth_gatemate: Remove specify blocks
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2021-11-13
Patrick Urban
synth_gatemate: Remove gatemate_bramopt pass
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2021-11-13
Patrick Urban
synth_gatemate: Apply new test practice with assert-max
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2021-11-13
Patrick Urban
synth_gatemate: Fix fsm test
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2021-11-13
Patrick Urban
synth_gatemate: Revise block RAM read modes and initial...
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2021-11-13
Patrick Urban
synth_gatemate: Remove unsupported FF initialization
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2021-11-13
Patrick Urban
synth_gatemate: Rename multiplier factor parameters
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