projects / yosys.git / shortlog
? search:
summary | shortlog | log | commit | commitdiff | tree
first ⋅ prev ⋅ next
yosys.git
2019-12-27 Eddie HungReally fix it! commit | commitdiff | tree
2019-12-27 Eddie Hungwrite_xaiger: fix arrival times for non boxes commit | commitdiff | tree
2019-12-23 Eddie HungDisable clock domain partitioning in Yosys pass, let... commit | commitdiff | tree
2019-12-23 Eddie Hungwrite_xaiger to opt instead of just clean whiteboxes commit | commitdiff | tree
2019-12-20 Eddie HungMerge remote-tracking branch 'origin/master' into xaig_dff commit | commitdiff | tree
2019-12-20 Eddie HungAdd abc9_arrival times for RAM{32,64}M commit | commitdiff | tree
2019-12-20 Eddie HungMerge remote-tracking branch 'origin/master' into xaig_dff commit | commitdiff | tree
2019-12-20 Eddie HungAdd RAM{32,64}M to abc9_map.v commit | commitdiff | tree
2019-12-20 Eddie HungPut specify/endspecify inside `` commit | commitdiff | tree
2019-12-20 Eddie HungMerge pull request #1585 from YosysHQ/eddie/fix_abc9_lut commit | commitdiff | tree
2019-12-20 Eddie HungMerge pull request #1587 from YosysHQ/revert-1558-eddie... commit | commitdiff | tree
2019-12-20 Eddie HungRevert "Optimise write_xaiger" commit | commitdiff | tree
2019-12-20 Graham EdgecombeFix linking with Python 3.8 commit | commitdiff | tree
2019-12-20 Graham EdgecombeAdd PYTHON_CONFIG variable to the Makefile commit | commitdiff | tree
2019-12-19 Eddie HungAdd RAM{32,64}M to abc9_map.v commit | commitdiff | tree
2019-12-19 Eddie HungSplit into $__ABC9_ASYNC[01], do not add cell->type... commit | commitdiff | tree
2019-12-19 Eddie HungMerge remote-tracking branch 'origin/master' into xaig_dff commit | commitdiff | tree
2019-12-19 Eddie HungMerge pull request #1581 from YosysHQ/clifford/fix1565 commit | commitdiff | tree
2019-12-19 Eddie HungMerge pull request #1558 from YosysHQ/eddie/xaiger_cleanup commit | commitdiff | tree
2019-12-19 Eddie HungMerge pull request #1569 from YosysHQ/eddie/fix_1531 commit | commitdiff | tree
2019-12-19 Eddie HungMerge pull request #1571 from YosysHQ/eddie/fix_1570 commit | commitdiff | tree
2019-12-19 Marcin Kościelnickixilinx: Add simulation models for remaining CLB primitives. commit | commitdiff | tree
2019-12-19 Marcin Kościelnickixilinx_dffopt: Keep order of LUT inputs. commit | commitdiff | tree
2019-12-18 Eddie HungBump ABC again commit | commitdiff | tree
2019-12-18 Eddie HungInterpret "abc9 -lut" as lut string only if [0-9:] commit | commitdiff | tree
2019-12-18 Eddie HungAdd "scratchpad" to CHANGELOG commit | commitdiff | tree
2019-12-18 Eddie HungMerge branch 'master' of github.com:YosysHQ/yosys commit | commitdiff | tree
2019-12-18 David ShahMerge pull request #1563 from YosysHQ/dave/async-prld commit | commitdiff | tree
2019-12-18 Eddie HungMerge pull request #1572 from nakengelhardt/scratchpad_pass commit | commitdiff | tree
2019-12-18 Eddie HungMerge pull request #1584 from YosysHQ/mwk/xilinx-flaky... commit | commitdiff | tree
2019-12-18 Marcin Kościelnickitests/xilinx: fix flaky mux test commit | commitdiff | tree
2019-12-18 Marcin Kościelnickixilinx: Add xilinx_dffopt pass (#1557) commit | commitdiff | tree
2019-12-18 Marcin Kościelnickixilinx: Improve flip-flop handling. commit | commitdiff | tree
2019-12-18 Clifford WolfSend people to symbioticeda.com instead of verific.com commit | commitdiff | tree
2019-12-18 N. Engelhardtuse extra_args commit | commitdiff | tree
2019-12-18 Eddie HungRemove &verify -s commit | commitdiff | tree
2019-12-18 Eddie HungBump ABC for upstream fix commit | commitdiff | tree
2019-12-18 Eddie HungUse pool<> instead of std::set<> to preserver ordering commit | commitdiff | tree
2019-12-17 Eddie Hungaiger frontend to user shorter, $-prefixed, names commit | commitdiff | tree
2019-12-17 Eddie HungCleanup xaiger, remove unnecessary complexity with... commit | commitdiff | tree
2019-12-17 Eddie Hungread_xaiger to cope with optional '\n' after 'c' commit | commitdiff | tree
2019-12-17 Clifford WolfFix sim for assignments with lhs<rhs size, fixes #1565 commit | commitdiff | tree
2019-12-17 Eddie HungCleanup commit | commitdiff | tree
2019-12-17 Eddie HungDo not sigmap commit | commitdiff | tree
2019-12-17 Eddie HungRevert "Use sigmap signal" commit | commitdiff | tree
2019-12-17 Eddie HungMerge pull request #1574 from YosysHQ/eddie/xilinx_lutram commit | commitdiff | tree
2019-12-17 Eddie HungMerge pull request #1521 from dh73/diego/memattr commit | commitdiff | tree
2019-12-17 Eddie Hungabc9 needs a clean afterwards commit | commitdiff | tree
2019-12-17 Eddie HungEnforce non-existence commit | commitdiff | tree
2019-12-17 Eddie HungPut $__ABC9_{FF_,ASYNC} into same clock domain as abc9_flop commit | commitdiff | tree
2019-12-17 Eddie HungUse sigmap signal commit | commitdiff | tree
2019-12-16 Eddie HungUpdate doc commit | commitdiff | tree
2019-12-16 Eddie HungSkip $inout transformation if not a PI commit | commitdiff | tree
2019-12-16 Eddie HungRevert "write_xaiger: use sigmap bits more consistently" commit | commitdiff | tree
2019-12-16 Eddie HungAdd another test commit | commitdiff | tree
2019-12-16 Eddie HungMore sloppiness, thanks @dh73 for spotting commit | commitdiff | tree
2019-12-16 Eddie HungAccidentally commented out tests commit | commitdiff | tree
2019-12-16 Eddie HungAdd unconditional match blocks for force RAM commit | commitdiff | tree
2019-12-16 Eddie HungOops commit | commitdiff | tree
2019-12-16 Eddie HungMerge blockram tests commit | commitdiff | tree
2019-12-16 Eddie HungUpdate xc7/xcu bram rules commit | commitdiff | tree
2019-12-16 Eddie HungImplement 'attributes' grammar commit | commitdiff | tree
2019-12-16 Eddie HungMerge branch 'diego/memattr' of https://github.com... commit | commitdiff | tree
2019-12-16 Eddie HungMerge branch 'eddie/xilinx_lutram' of github.com:YosysH... commit | commitdiff | tree
2019-12-16 Eddie HungPopulate DID/DOD even if unused commit | commitdiff | tree
2019-12-16 Eddie HungRename *RAM{32,64}M rules to RAM{32X2,64X1}Q commit | commitdiff | tree
2019-12-16 Eddie Hungwrite_xaiger: use sigmap bits more consistently commit | commitdiff | tree
2019-12-16 Diego HFixing compiler warning/issues. Moving test script... commit | commitdiff | tree
2019-12-16 N. Engelhardtadd assert option to scratchpad command commit | commitdiff | tree
2019-12-16 Diego HRemoving fixed attribute value to !ramstyle rules commit | commitdiff | tree
2019-12-16 Diego HMerging attribute rules into a single match block;... commit | commitdiff | tree
2019-12-16 Eddie HungMerge pull request #1575 from rodrigomelo9/master commit | commitdiff | tree
2019-12-16 Eddie HungMerge pull request #1577 from gromero/for-yosys commit | commitdiff | tree
2019-12-16 Eddie HungMerge pull request #1578 from noopwafel/eqneq-debug commit | commitdiff | tree
2019-12-15 Alyssa MilburnFix opt_expr.eqneq.cmpzero debug print commit | commitdiff | tree
2019-12-14 Eddie HungName inputs/outputs of aiger 'i%d' and 'o%d' commit | commitdiff | tree
2019-12-13 Diego HRefactoring memory attribute matching based on IEEE... commit | commitdiff | tree
2019-12-13 Eddie HungMerge pull request #1533 from dh73/bram_xilinx commit | commitdiff | tree
2019-12-13 Eddie HungDisable RAM16X1D test commit | commitdiff | tree
2019-12-13 Eddie HungDisable RAM16X1D match rule; carry-over from LUT4 arches commit | commitdiff | tree
2019-12-13 Eddie HungRAM64M8 to also have [5:0] for address commit | commitdiff | tree
2019-12-13 Diego HRenaming BRAM memory tests for the sake of uniformity commit | commitdiff | tree
2019-12-13 Rodrigo Alejandro... Fixed some missing "verilog_" in documentation commit | commitdiff | tree
2019-12-13 N. Engelhardtadd periods and newlines to help message commit | commitdiff | tree
2019-12-13 Eddie HungRemove extraneous synth_xilinx call commit | commitdiff | tree
2019-12-13 Eddie HungAdd tests for these new models commit | commitdiff | tree
2019-12-13 Eddie HungAdd RAM32X6SDP and RAM64X3SDP modes commit | commitdiff | tree
2019-12-13 Eddie HungFix RAM64M model to have 6 bit address bus commit | commitdiff | tree
2019-12-13 Eddie HungAdd #1460 testcase commit | commitdiff | tree
2019-12-13 Eddie HungAdd memory rules for RAM16X1D, RAM32M, RAM64M commit | commitdiff | tree
2019-12-13 Eddie HungRename memory tests to lutram, add more xilinx tests commit | commitdiff | tree
2019-12-12 Diego HFixing citation in xc7_xcu_brams.txt file. Fixing RAMB3... commit | commitdiff | tree
2019-12-12 Eddie HungRemove 'clkpart' entry in CHANGELOG commit | commitdiff | tree
2019-12-12 Eddie HungMerge remote-tracking branch 'origin/master' into xaig_dff commit | commitdiff | tree
2019-12-12 Eddie Hungabc9_map.v: fix Xilinx LUTRAM commit | commitdiff | tree
2019-12-12 Eddie Hungabc9_map.v: fix Xilinx LUTRAM commit | commitdiff | tree
2019-12-12 Diego HAdding a note (TODO) in the memory_params.ys check... commit | commitdiff | tree
2019-12-12 N. Engelhardtadd test and make help message more verbose commit | commitdiff | tree
2019-12-12 Diego HUpdating RAMB36E1 thresholds. Adding test for both... commit | commitdiff | tree
2019-12-12 Diego HMerge https://github.com/YosysHQ/yosys into bram_xilinx commit | commitdiff | tree
next