| 2019-04-18 | 
whitequark | hdl.xfrm: handle classes that inherit from Record. | 
commit | commitdiff | tree | 
| 2019-04-15 | 
whitequark | lib.io: rework TSTriple/Tristate interface to use pin_l...  | 
commit | commitdiff | tree | 
| 2019-04-10 | 
whitequark | hdl.ast: fix some type checks. | 
commit | commitdiff | tree | 
| 2019-04-10 | 
whitequark | hdl.xfrm: allow using FragmentTransformer on any elabor...  | 
commit | commitdiff | tree | 
| 2019-04-09 | 
whitequark | hdl: remove deprecated get_fragment() and lower() methods. | 
commit | commitdiff | tree | 
| 2019-04-03 | 
whitequark | hdl.ast: handle a common typo, such as Signal(1, True). | 
commit | commitdiff | tree | 
| 2019-03-28 | 
whitequark | test_sim: add missing add_process(). | 
commit | commitdiff | tree | 
| 2019-03-28 | 
Luke Wren | lib.cdc: add optional reset to MultiReg, and document...  | 
commit | commitdiff | tree | 
| 2019-03-28 | 
whitequark | back.rtlil: fix off-by-one in Part legalization. | 
commit | commitdiff | tree | 
| 2019-03-25 | 
anuejn | hdl.rec: separate record and signal name with __, not _. | 
commit | commitdiff | tree | 
| 2019-03-25 | 
whitequark | hdl.ast: fix typo. | 
commit | commitdiff | tree | 
| 2019-03-12 | 
Alain Péteut | examples.por: fix typo | 
commit | commitdiff | tree | 
| 2019-03-03 | 
whitequark | lib.fifo: register GrayEncoder output before CDC. | 
commit | commitdiff | tree | 
| 2019-03-03 | 
whitequark | tracer: factor out get_var_name(default=). | 
commit | commitdiff | tree | 
| 2019-03-03 | 
whitequark | hdl.rec: remove __slots__. | 
commit | commitdiff | tree | 
| 2019-02-22 | 
Alain Péteut | setup.py: constrain Python version | 
commit | commitdiff | tree | 
| 2019-02-14 | 
whitequark | hdl.ir: raise a more descriptive error on non-elaborata...  | 
commit | commitdiff | tree | 
| 2019-01-26 | 
whitequark | back.rtlil: accept ast.Const as cell parameter. | 
commit | commitdiff | tree | 
| 2019-01-26 | 
whitequark | hdl.ast: fix ValueKey for Cat. | 
commit | commitdiff | tree | 
| 2019-01-26 | 
whitequark | compat.fhdl.module: fix typo. | 
commit | commitdiff | tree | 
| 2019-01-26 | 
whitequark | compat.fhdl.specials: fix __all__ list. | 
commit | commitdiff | tree | 
| 2019-01-26 | 
whitequark | compat.genlib.resetsync: add shim for AsyncResetSynchro...  | 
commit | commitdiff | tree | 
| 2019-01-26 | 
whitequark | compat.fifo: fix _FIFOInterface deprecation wrapper. | 
commit | commitdiff | tree | 
| 2019-01-26 | 
whitequark | lib.cdc: add ResetSynchronizer. | 
commit | commitdiff | tree | 
| 2019-01-26 | 
whitequark | back.pysim: support async reset. | 
commit | commitdiff | tree | 
| 2019-01-26 | 
whitequark | back.pysim: give better names to unnamed fragments...  | 
commit | commitdiff | tree | 
| 2019-01-26 | 
whitequark | examples: update for newer API. | 
commit | commitdiff | tree | 
| 2019-01-26 | 
whitequark | back.rtlil: accept any elaboratable, not just fragments. | 
commit | commitdiff | tree | 
| 2019-01-26 | 
whitequark | compat: suppress deprecation warnings that are internal...  | 
commit | commitdiff | tree | 
| 2019-01-26 | 
whitequark | test.compat: reenable tests converting to Verilog. | 
commit | commitdiff | tree | 
| 2019-01-26 | 
whitequark | compat.sim: fix deprecated stdlib import. | 
commit | commitdiff | tree | 
| 2019-01-26 | 
whitequark | hdl.ir: rename .get_fragment() to .elaborate(). | 
commit | commitdiff | tree | 
| 2019-01-26 | 
whitequark | test.compat: import tests from Migen as appropriate. | 
commit | commitdiff | tree | 
| 2019-01-26 | 
whitequark | hdl.ast: fix shape calculation for *. | 
commit | commitdiff | tree | 
| 2019-01-25 | 
whitequark | back.pysim: fix behavior of initial cycle for sync...  | 
commit | commitdiff | tree | 
| 2019-01-22 | 
whitequark | lib.fifo: in FIFOInterface.read(), check readable on...  | 
commit | commitdiff | tree | 
| 2019-01-22 | 
whitequark | compat.genlib.fifo: adjust _FIFOInterface shim to not...  | 
commit | commitdiff | tree | 
| 2019-01-22 | 
whitequark | lib.fifo: fix typo in AsyncFIFO documentation. | 
commit | commitdiff | tree | 
| 2019-01-21 | 
whitequark | lib.fifo: add AsyncFIFO and AsyncFIFOBuffered. | 
commit | commitdiff | tree | 
| 2019-01-21 | 
whitequark | back.pysim: wake up processes before ever committing...  | 
commit | commitdiff | tree | 
| 2019-01-20 | 
whitequark | compat.genlib.cdc: add missing import. | 
commit | commitdiff | tree | 
| 2019-01-20 | 
whitequark | compat.genlib.cdc: add GrayCounter and GrayDecoder...  | 
commit | commitdiff | tree | 
| 2019-01-20 | 
whitequark | lib.coding: add GrayEncoder and GrayDecoder. | 
commit | commitdiff | tree | 
| 2019-01-20 | 
whitequark | lib.coding: add width as attribute to all coders. | 
commit | commitdiff | tree | 
| 2019-01-19 | 
whitequark | lib.fifo: use memory in the FIFO model. | 
commit | commitdiff | tree | 
| 2019-01-19 | 
whitequark | lib.fifo: use model equivalence to simplify formal...  | 
commit | commitdiff | tree | 
| 2019-01-19 | 
whitequark | hdl.ast: implement shape for modulo operator. | 
commit | commitdiff | tree | 
| 2019-01-19 | 
whitequark | hdl.ast: add Value.implies. | 
commit | commitdiff | tree | 
| 2019-01-19 | 
whitequark | hdl.xfrm: mark internal registers used in lowering...  | 
commit | commitdiff | tree | 
| 2019-01-19 | 
whitequark | doc: update COMPAT_SUMMARY. | 
commit | commitdiff | tree | 
| 2019-01-19 | 
whitequark | fhdl.specials: add compatibility shim for Tristate. | 
commit | commitdiff | tree | 
| 2019-01-19 | 
whitequark | lib.fifo: fix simulation read/write methods to take...  | 
commit | commitdiff | tree | 
| 2019-01-19 | 
whitequark | compat.genlib.fifo: add aliases for SyncFIFO, SyncFIFOB...  | 
commit | commitdiff | tree | 
| 2019-01-19 | 
whitequark | lib.fifo: formally verify FIFO contract. | 
commit | commitdiff | tree | 
| 2019-01-19 | 
whitequark | hdl.ast: give Assert and Assume their own src_loc. | 
commit | commitdiff | tree | 
| 2019-01-18 | 
whitequark | back.rtlil: only emit each AnyConst/AnySeq cell once. | 
commit | commitdiff | tree | 
| 2019-01-17 | 
Alain Péteut | cli: add missing default for `generate` | 
commit | commitdiff | tree | 
| 2019-01-17 | 
whitequark | lib.fifo: add basic formal specification. | 
commit | commitdiff | tree | 
| 2019-01-17 | 
whitequark | hdl.ast: allow sampling ClockSignal, ResetSignal. | 
commit | commitdiff | tree | 
| 2019-01-17 | 
whitequark | hdl.ast: add Past, Stable, Rose, Fell. | 
commit | commitdiff | tree | 
| 2019-01-17 | 
whitequark | formal: extract from toplevel module. | 
commit | commitdiff | tree | 
| 2019-01-17 | 
whitequark | hdl.xfrm: add SampleLowerer. | 
commit | commitdiff | tree | 
| 2019-01-17 | 
whitequark | hdl.ast: add Sample. | 
commit | commitdiff | tree | 
| 2019-01-16 | 
whitequark | lib.fifo: port sync FIFO queues from Migen. | 
commit | commitdiff | tree | 
| 2019-01-16 | 
whitequark | hdl.ast: fix naming of Signal.like() signals when trace...  | 
commit | commitdiff | tree | 
| 2019-01-16 | 
whitequark | back.rtlil: slightly nicer naming for $next signals...  | 
commit | commitdiff | tree | 
| 2019-01-16 | 
whitequark | back.rtlil: rename \sig$next to $next$sig. | 
commit | commitdiff | tree | 
| 2019-01-16 | 
whitequark | Travis: install SymbiYosys and Yices2. | 
commit | commitdiff | tree | 
| 2019-01-15 | 
whitequark | Unbreak 655d02d5. | 
commit | commitdiff | tree | 
| 2019-01-15 | 
William D....  | back.rtlil: Generate $anyconst and $anyseq cells. | 
commit | commitdiff | tree | 
| 2019-01-15 | 
William D....  | hdl.xfrm: Add on_AnyConst and on_AnySeq abstract method...  | 
commit | commitdiff | tree | 
| 2019-01-15 | 
William D....  | hdl.ast: Add AnyConst and AnySeq value types. | 
commit | commitdiff | tree | 
| 2019-01-15 | 
Sebastien Bourdeauducq | README: add LambdaConcept sponsorship | 
commit | commitdiff | tree | 
| 2019-01-14 | 
whitequark | lib.io: pass pin to platform.get_tristate(). | 
commit | commitdiff | tree | 
| 2019-01-14 | 
whitequark | hdl.ir: allow explicitly requesting flattening. | 
commit | commitdiff | tree | 
| 2019-01-14 | 
whitequark | lib.io: lower to platform-independent tristate buffer. | 
commit | commitdiff | tree | 
| 2019-01-14 | 
whitequark | hdl: make ClockSignal and ResetSignal usable on LHS. | 
commit | commitdiff | tree | 
| 2019-01-13 | 
whitequark | hdl.dsl: cases wider than switch test value are unreach...  | 
commit | commitdiff | tree | 
| 2019-01-13 | 
whitequark | hdl.dsl: accept (but warn on) cases wider than switch...  | 
commit | commitdiff | tree | 
| 2019-01-13 | 
whitequark | back.pysim: handle non-driven, non-port signals. | 
commit | commitdiff | tree | 
| 2019-01-13 | 
whitequark | back.verilog: better error message if Yosys is not...  | 
commit | commitdiff | tree | 
| 2019-01-08 | 
whitequark | back.verilog: remove undriven check. | 
commit | commitdiff | tree | 
| 2019-01-06 | 
Adam Greig | Give the top level scope a name to fix VCD hierarchy. | 
commit | commitdiff | tree | 
| 2019-01-02 | 
whitequark | hdl.ast: allow slicing [n:n] into n-bit value. | 
commit | commitdiff | tree | 
| 2019-01-02 | 
whitequark | back.rtlil: translate empty slices correctly. | 
commit | commitdiff | tree | 
| 2019-01-02 | 
William D....  | back.rtlil: Generate RTLIL for Assert/Assume statements. | 
commit | commitdiff | tree | 
| 2019-01-02 | 
William D....  | hdl.xfrm: Add Assert and Assume abstract methods for...  | 
commit | commitdiff | tree | 
| 2019-01-02 | 
William D....  | hdl.dsl: Support Assert and Assume where an Assign...  | 
commit | commitdiff | tree | 
| 2019-01-02 | 
William D....  | hdl.ast: Add Assert and Assign statements. | 
commit | commitdiff | tree | 
| 2019-01-01 | 
whitequark | hdl.ast: experimentally add Value._as_const. | 
commit | commitdiff | tree | 
| 2019-01-01 | 
whitequark | back.rtlil: fix typo. | 
commit | commitdiff | tree | 
| 2019-01-01 | 
whitequark | hdl.rec: include record name in error message. | 
commit | commitdiff | tree | 
| 2019-01-01 | 
whitequark | hdl.rec: use a helpful error on unknown field reference. | 
commit | commitdiff | tree | 
| 2019-01-01 | 
whitequark | hdl.mem: add DummyPort, for testing and verification. | 
commit | commitdiff | tree | 
| 2018-12-31 | 
whitequark | back.rtlil: match shape of Array elements to ArrayProxy...  | 
commit | commitdiff | tree | 
| 2018-12-31 | 
whitequark | back.rtlil: fix typo. | 
commit | commitdiff | tree | 
| 2018-12-29 | 
whitequark | lib.cdc: fix tests to actually run. | 
commit | commitdiff | tree | 
| 2018-12-29 | 
whitequark | back.pysim: warn if simulation is not run. | 
commit | commitdiff | tree | 
| 2018-12-28 | 
whitequark | hdl.rec: add basic record support. | 
commit | commitdiff | tree | 
| 2018-12-28 | 
whitequark | tracer: factor out get_src_loc(). | 
commit | commitdiff | tree | 
| next |