gem5.git
2011-04-17 Nathan Binkertstyle: fix all_regions code and remove bogus region...
2011-04-17 Nathan Binkertstyle: remove extra debugging print
2011-04-17 Nathan Binkertfile_types: Make code work in Python 2.4
2011-04-15 Nathan Binkertunittest: Make unit tests capable of using swig and...
2011-04-15 Nathan Binkertpython: cleanup python code so stuff doesn't automatica...
2011-04-15 Nathan Binkertscons: make a flexible system for guarding source files
2011-04-15 Nathan Binkerttrace: reimplement the DTRACE function so it doesn...
2011-04-15 Nathan Binkertdebug: create a Debug namespace
2011-04-15 Nathan Binkertincludes: fix up code after sorting
2011-04-15 Nathan Binkertincludes: sort all includes
2011-04-15 Nathan Binkertstyle: add sort_includes to the style hook
2011-04-15 Nathan Binkertstyle: move style verifiers into classes
2011-04-15 Nathan Binkertstyle: add a user interface wrapper class
2011-04-15 Nathan Binkertutil: python implementation of a routine that will...
2011-04-15 Nathan Binkertregion: add a utility class for keeping track of region...
2011-04-15 Nathan BinkertSortedDict: add functions for getting ranges of keys...
2011-04-15 Nathan Binkertpython: figure out if the m5.internal package exists...
2011-04-13 Nathan Binkertrefcnt: Update doxygen comments
2011-04-13 Nathan Binkertrefcnt: Inline comparison functions
2011-04-13 Nathan Binkertmain: separate out interact() so it can be used by...
2011-04-13 Nathan Binkertutil: fix the language type function
2011-04-12 Ali SaidiARM: Fix stats for ARM_SE checkpoint restore fix.
2011-04-11 Ali SaidiARM: Fix checkpoint restoration in ARM_SE.
2011-04-11 Ali SaidiARM: Get rid of some comments/todos that no longer...
2011-04-06 Brad Beckmannruby: fixes to support more types of RubyRequests
2011-04-04 Ali SaidiARM: Update stats for default inclusion of CF adapter.
2011-04-04 Ali SaidiARM: Include IDE/CF controller by default in PBX model.
2011-04-04 Anthony GutierrezSim: Fix Simulation.py to allow more than 1 core for...
2011-04-04 Ali SaidiARM: Update stats for previous changes.
2011-04-04 Ali SaidiARM: Use CPU local lock before sending load to mem...
2011-04-04 Ali SaidiARM: Fix checkpoint restoration into O3 CPU and the...
2011-04-04 Ali SaidiARM: Fix bug in MicroLdrNeon templates for initiateAcc().
2011-04-04 William WangARM: Cleanup and small fixes to some NEON ops to match...
2011-04-04 Ali SaidiARM: Cleanup implementation of ITSTATE and put importan...
2011-04-04 Ali SaidiARM: Fix m5op parameters bug.
2011-04-04 Ali SaidiARM: Tag appropriate instructions as IsReturn
2011-04-04 Ali SaidiARM: Fix table walk going on while ASID changes error
2011-04-04 Ali SaidiCPU: Remove references to memory copy operations
2011-04-04 Ali SaidiO3: Update stats for memory order violation checking...
2011-04-04 Ali SaidiO3: Tighten memory order violation checking to 16 bytes.
2011-04-04 Ali SaidiIDE: Support x86, Alpha, and ARM use of the IDE controller.
2011-04-04 Ali SaidiARM: Fix checkpointing case where PL111 is powered...
2011-04-04 Ali SaidiARM: Remove debugging warn that was accidently left in.
2011-04-04 Ali SaidiARM: Fix multiplication error in udelay
2011-04-01 Brad Beckmannhammer: fixed dma uniproc error
2011-04-01 Lisa HsuCacheMemory: add allocateVoid() that is == allocate...
2011-04-01 Lisa HsuRuby: Simplify SLICC and Entry/TBE handling.
2011-04-01 Lisa HsuRuby: Add new object called WireBuffer to mimic a Wire.
2011-04-01 Lisa HsuRuby: have the rubytester pass contextId to Ruby.
2011-04-01 Lisa HsuRuby: enable multiple sequencers in one controller.
2011-04-01 Lisa HsuRuby: pass Packet->Req->contextId() to Ruby.
2011-03-31 Lisa HsuRuby: Bug in SLICC forgot semicolon at end of code.
2011-03-29 Korey Sewellsim: typecast Tick to UTick for eventQ assert
2011-03-29 Gabe BlackPower: Fix compilation.
2011-03-28 Somayeh SardashtiThis patch supports cache flushing in MOESI_hammer
2011-03-28 Nilay VaishConfig: Import math in MI_example.py
2011-03-27 Steve Reinhardttests: update reference outputs for ruby cache index...
2011-03-26 Korey Sewellmips: cleanup ISA-specific code
2011-03-25 Brad Beckmannruby: fixed cache index setting
2011-03-25 Gabe BlackArm: Add in a missing miscRegName.
2011-03-24 Gabe BlackArm: Get rid of unused and incomplete setCp15Register...
2011-03-24 Gabe BlackArm: Get rid of the unused copyStringArray32 method...
2011-03-24 Gabe BlackISA parser: Set up op_src_decl and op_dest_decl for...
2011-03-23 Tushar KrishnaThis patch fixes a build error in networktest.cc that...
2011-03-22 Nilay VaishRuby: Remove CacheMsg class from SLICC
2011-03-22 Tushar KrishnaThis patch makes garnet use the info about active and...
2011-03-22 Tushar Krishnafix garnet fleible pipeline
2011-03-22 Tushar KrishnaThis patch adds the network tester for simple and garne...
2011-03-20 Nilay VaishSLICC: Remove WakeUp* import calls from ast/__init__.py
2011-03-20 Lisa Hsuconfigs: combine ruby_se.py and se.py to avoid all...
2011-03-20 Lisa Hsuenable x86 workloads on se.py
2011-03-20 Lisa Hsuse.py: Modify script to make multiprogramming much...
2011-03-20 Lisa Hsuutil: update aggregator to handle x86 checkpoints.
2011-03-19 Nilay VaishRuby: Convert CacheRequestType to RubyRequestType
2011-03-19 Nilay VaishRuby: Convert AccessModeType to RubyAccessMode
2011-03-19 Brad BeckmannMOESI_hammer: minor fixes to full-bit dir
2011-03-19 Brad BeckmannRuby: dma retry fix
2011-03-19 Brad BeckmannRubyPort: minor fixes to trace flag and dprintfs
2011-03-19 Brad Beckmannruby: added useful dma progress dprintf
2011-03-19 Brad Beckmannslicc: improved invalid transition message
2011-03-19 Brad BeckmannMOESI_hammer: fixed dma bug with shared data
2011-03-19 Brad BeckmannMOESI_CMP_directory: significant dma bug fixes
2011-03-18 Nilay VaishSLICC: Remove external_type for structures
2011-03-18 Nilay VaishSLICC: Remove the keyword wake_up_dependents
2011-03-18 Nilay VaishSLICC: Remove the keyword wake_up_all_dependents
2011-03-18 Steve Reinhardtswig: get rid of m5.internal.random module (swig/random.i)
2011-03-18 Steve Reinhardtbase: disable FastAlloc in debug builds by default
2011-03-18 Ali SaidiAutomated merge with ssh://hg@repo.m5sim.org/m5
2011-03-18 Ali SaidiARM: Update stats for the previous changes and add...
2011-03-18 Chris EmmonsARM: Add minimal ARM_SE support for m5threads.
2011-03-18 Ali SaidiARM: Fix subtle bug in LDM.
2011-03-18 Ali SaidiARM: Implement the Instruction Set Attribute Registers...
2011-03-18 Ali SaidiARM: Identify branches as conditional or unconditional...
2011-03-18 Ali SaidiARM: Bare metal system should have 256MB of RAM.
2011-03-18 Ali SaidiARM: Fix small bug with VLDM/VSTM instructions.
2011-03-18 Ali SaidiARM: Detect and skip udelay() functions in linux kernel.
2011-03-18 Ali SaidiARM: Allow conditional quiesce instructions.
2011-03-18 Ali SaidiStats: Update the statistics for rfe patch.
2011-03-18 Matt HorsnellARM: Fix RFE macrop.
2011-03-18 Matt HorsnellARM: Rename registers used as temporary state by microops.
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