yosys.git
2020-12-22 whitequarkMerge pull request #2491 from zachjs/port-bind-sign
2020-12-22 Yosys BotBump version
2020-12-21 Marcelina Kościelnickaxilinx: Add some missing blackbox cells.
2020-12-21 Marcelina Kościelnickaxilinx: Regenerate cells_xtra.v using Vivado 2020.2
2020-12-21 whitequarkMerge pull request #2496 from whitequark/cxxrtl-fixes
2020-12-21 whitequarkcxxrtl: speed up bit repeats (sign extends, etc).
2020-12-21 whitequarkcxxrtl: speed up commits on clang.
2020-12-20 whitequarkcxxrtl: use `static inline` instead of `inline` in...
2020-12-20 Yosys BotBump version
2020-12-19 whitequarkMerge pull request #2487 from whitequark/cxxrtl-outlining
2020-12-19 Zachary SnowSign extend port connections where necessary
2020-12-18 Yosys BotBump version
2020-12-17 Marcelina Kościelnickaxilinx: Add FDDRCPE and FDDRRSE blackbox cells.
2020-12-15 whitequarkcxxrtl: print names of cells inlined in connections.
2020-12-15 whitequarkcxxrtl: disable optimization of debug_items().
2020-12-15 whitequarkcxxrtl: make alias analysis outlining-aware.
2020-12-15 Yosys BotBump version
2020-12-14 Marcelina Kościelnickatiminginfo: Error instead of segfault on const signals.
2020-12-14 whitequarkcxxrtl: add a "bare minimum" debug information level.
2020-12-14 whitequarkcxxrtl: implement debug information outlining.
2020-12-13 whitequarkcxxrtl: rename "elision" to "inlining". NFC.
2020-12-13 whitequarkcxxrtl: fix outdated comment. NFC.
2020-12-13 whitequarkcxxrtl: use IdString::isPublic(). NFC.
2020-12-13 Yosys BotBump version
2020-12-12 whitequarkkernel: make IdString::isPublic() const.
2020-12-12 whitequarkMerge pull request #2485 from whitequark/cxxrtl-cell...
2020-12-11 whitequarkcxxrtl: don't overwrite buffered inputs.
2020-12-10 Yosys BotBump version
2020-12-09 Miodrag MilanovićMerge pull request #2483 from YosysHQ/pmgen_nice_error
2020-12-09 Miodrag MilanovicReturn nice error in pmgen generated code, fixes #2482
2020-12-09 Yosys BotBump version
2020-12-08 whitequarkMerge pull request #2478 from whitequark/improve-bugpoint
2020-12-07 whitequarkbugpoint: add -wires option.
2020-12-07 whitequarkbugpoint: try to remove whole processes first.
2020-12-07 whitequarkbugpoint: accept quoted strings in -grep.
2020-12-07 whitequarkbugpoint: add -command option.
2020-12-04 Yosys BotBump version
2020-12-03 whitequarkMerge pull request #2470 from whitequark/cxxrtl-create_at
2020-12-03 whitequarkcxxrtl: allow customizing the root module path in the...
2020-12-03 Yosys BotBump version
2020-12-02 whitequarkMerge pull request #2468 from whitequark/cxxrtl-assert
2020-12-02 whitequarkMerge pull request #2469 from whitequark/cxxrtl-no-clk
2020-12-02 whitequarkMerge pull request #2466 from whitequark/cxxrtl-reset
2020-12-02 whitequarkMerge pull request #2456 from Zottel/master
2020-12-02 whitequarkMerge pull request #2455 from gsomlo/gls-fedpkg-fixes
2020-12-02 David ShahMerge pull request #2467 from YosysHQ/dave/nexus-carry-fix
2020-12-02 whitequarkcxxrtl: fix crashes caused by a floating or constant...
2020-12-02 whitequarkMerge pull request #2446 from RobertBaruch/rtlil_format
2020-12-02 whitequarkcxxrtl: use CXXRTL_ASSERT for RTL contract violations...
2020-12-02 David Shahnexus: More efficient CO mapping
2020-12-02 Miodrag MilanovicBump required Verific version
2020-12-02 whitequarkcxxrtl: provide a way to perform unobtrusive power...
2020-12-02 Yosys BotBump version
2020-12-01 Claire XenMerge pull request #2463 from georgerennie/fix_verilog_...
2020-12-01 Miodrag MilanovićMerge pull request #2460 from pepijndevos/simple-gowin
2020-12-01 georgerennieFix SYNTHESIS always being defined in Verilog frontend
2020-11-30 Pepijn de Vosadd -noalu and -json option for apicula
2020-11-26 Julius RoobReturn correct modname when found in cache.
2020-11-26 Gabriel Somlofixup over commit 829b5cca to re-enable ABCEXTERNAL...
2020-11-26 Gabriel SomloAdd #include needed to build with gcc-11
2020-11-26 Yosys BotBump version
2020-11-25 whitequarkMerge pull request #2452 from whitequark/rtlil-remove...
2020-11-25 Robert BaruchFurther juggles the wording of "character".
2020-11-25 Robert BaruchClarifies how character encodings work.
2020-11-25 Miodrag MilanovićMerge pull request #2453 from YosysHQ/mmicko/verilog_as...
2020-11-25 Robert BaruchClarifies whitespace and eol.
2020-11-25 Robert BaruchCleans up doublequotes
2020-11-25 Robert BaruchClarifies use of integers, and character set.
2020-11-25 Miodrag MilanovicAdd verilog backend option for simple_lhs
2020-11-25 Robert BaruchClarifies processes, corrects some attributes
2020-11-25 whitequarkrtlil: remove dotted identifiers.
2020-11-25 Miodrag Milanovicgenerate only simple assignments in verilog backend
2020-11-25 Claire XenMerge pull request #2133 from dh73/nodev_head
2020-11-25 Robert BaruchRefactors for attributes.
2020-11-25 whitequarkMerge pull request #2442 from cr1901/sccache
2020-11-25 whitequarkMerge pull request #2450 from nitz/sim-vcd-filename
2020-11-25 William D.... Makefile: Update ABCREV to bring in sccache fixes.
2020-11-25 Yosys BotBump version
2020-11-24 Robert BaruchCleans up some descriptions and syntax
2020-11-24 Chris DaileyAdd rewrite_filename for sim -vcd argument.
2020-11-24 whitequarkMerge pull request #2428 from whitequark/check-processes
2020-11-24 Miodrag MilanovićMerge pull request #2448 from nitz/tcl-script-documenta...
2020-11-24 Miodrag MilanovićMerge pull request #2295 from epfl-vlsc/firrtl_blackbox...
2020-11-24 nitztcl -h message only if YOSYS_ENABLE_TCL defined.
2020-11-23 Sahand KashaniFormatting fixes
2020-11-23 Robert BaruchAdds missing "end" and eol to module.
2020-11-23 Robert BaruchUpdate to Values #2
2020-11-23 Robert BaruchUpdate to Values section
2020-11-22 Robert BaruchAdds appendix on RTLIL text format
2020-11-21 Yosys BotBump version
2020-11-20 Miodrag MilanovićMerge pull request #2443 from YosysHQ/dave/nexus-mult...
2020-11-20 David Shahnexus: DSP inference support
2020-11-19 William D.... Makefile: Add disabled-by-default ENABLE_SCCACHE config...
2020-11-19 Yosys BotBump version
2020-11-18 Miodrag MilanovićMerge pull request #2441 from YosysHQ/dave/nexus_dsp_sim
2020-11-18 David Shahnexus: Add DSP simulation model
2020-11-18 Miodrag MilanovicFix duplicated parameter name typo
2020-11-17 Yosys BotBump version
2020-11-16 William Woodruffbackends/blif: Remove unused vector of strings (#2420)
2020-11-16 Miodrag MilanovićMerge pull request #2438 from kbeckmann/gowin_rpll
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