projects / yosys.git / shortlog
? search:
summary | shortlog | log | commit | commitdiff | tree
first ⋅ prev ⋅ next
yosys.git
2014-07-19 Clifford WolfMore verbose memory_share help message commit | commitdiff | tree
2014-07-19 Clifford WolfAdded SAT-based write-port sharing to memory_share commit | commitdiff | tree
2014-07-19 Clifford WolfAdded ModWalker helper class commit | commitdiff | tree
2014-07-19 Clifford WolfSome "const" cleanups in SigMap commit | commitdiff | tree
2014-07-19 Clifford WolfFixed bug in memory_share feedback-to-en code commit | commitdiff | tree
2014-07-18 Clifford WolfAdded translation from read-feedback to en-signals... commit | commitdiff | tree
2014-07-18 Clifford WolfImproved seeding of color rng in show command commit | commitdiff | tree
2014-07-18 Clifford WolfOnly create collision detect logic in memory_share... commit | commitdiff | tree
2014-07-18 Clifford WolfBugfix in tests/memories/run-test.sh commit | commitdiff | tree
2014-07-18 Clifford Wolfadded tests/memories commit | commitdiff | tree
2014-07-18 Clifford WolfAdded memory_share commit | commitdiff | tree
2014-07-18 Clifford WolfAdded automatic conversion from RTLIL::SigSpec to std... commit | commitdiff | tree
2014-07-18 Clifford WolfApply opt_reduce WR_EN opts to the whole mux tree drivi... commit | commitdiff | tree
2014-07-18 Clifford WolfAdded function-like cell creation helpers commit | commitdiff | tree
2014-07-18 Clifford WolfAdded log_id() helper function commit | commitdiff | tree
2014-07-17 Clifford WolfAlso simulate unmapped memories in "make test" commit | commitdiff | tree
2014-07-17 Clifford WolfImplemented dynamic bit-/part-select for memory writes commit | commitdiff | tree
2014-07-17 Clifford WolfFixed simlib.v model for $mem commit | commitdiff | tree
2014-07-17 Clifford WolfAdded support for bit/part select to mem2reg rewriter commit | commitdiff | tree
2014-07-17 Clifford WolfAdded support for constant bit- or part-select for... commit | commitdiff | tree
2014-07-17 Clifford WolfImproved opt_reduce handling of mem wr_en mux bits commit | commitdiff | tree
2014-07-17 Clifford WolfFixed RTLIL::SigSpec::append_bit() for appending constants commit | commitdiff | tree
2014-07-17 Clifford WolfAdded support for "blackbox" attribute to iopadmap commit | commitdiff | tree
2014-07-17 Clifford WolfAdded support for "blackbox" attribute to flatten/techmap commit | commitdiff | tree
2014-07-16 Clifford WolfAdded "inout" ports support to read_liberty commit | commitdiff | tree
2014-07-16 Clifford WolfSet blackbox attribute in "read_liberty -lib" commit | commitdiff | tree
2014-07-16 Clifford WolfFixed spelling of "direction" in read_liberty messages commit | commitdiff | tree
2014-07-16 Clifford WolfMerged new $mem/$memwr WR_EN interface commit | commitdiff | tree
2014-07-16 Clifford WolfChanged tests/techmap/mem_simple_4x1_map for new $mem... commit | commitdiff | tree
2014-07-16 Clifford Wolfimproved opt_reduce for $mem/$memwr WR_EN multiplexers commit | commitdiff | tree
2014-07-16 Clifford Wolfchanges in verilog frontend for new $mem/$memwr WR_EN... commit | commitdiff | tree
2014-07-16 Clifford WolfChanges to "memory" pass for new $memwr/$mem WR_EN... commit | commitdiff | tree
2014-07-16 Clifford WolfUpdated simlib to new $mem/$memwr interface commit | commitdiff | tree
2014-07-16 Clifford WolfChanged the $mem/$memwr WR_EN input to a per-data-bit... commit | commitdiff | tree
2014-07-16 Clifford WolfAdded note to "make test": use git checkout of iverilog commit | commitdiff | tree
2014-07-12 Clifford WolfAdded passing of various options to vhdl2verilog commit | commitdiff | tree
2014-07-11 Clifford WolfUse "verilog -sv" to parse .sv files commit | commitdiff | tree
2014-07-11 Clifford WolfFixed processing of initial values for block-local... commit | commitdiff | tree
2014-07-05 Clifford Wolfnow ignore init attributes on non-register wires in... commit | commitdiff | tree
2014-07-02 Clifford Wolffixed parsing of constant with comment between size... commit | commitdiff | tree
2014-07-02 Clifford Wolfsmall changes in presentation commit | commitdiff | tree
2014-06-29 Clifford WolfTiny fix in presentation commit | commitdiff | tree
2014-06-29 Clifford WolfProgress in presentation commit | commitdiff | tree
2014-06-28 Clifford WolfAdded links to some liberty files to README commit | commitdiff | tree
2014-06-26 Clifford WolfProgress in presentation commit | commitdiff | tree
2014-06-25 Clifford WolfFixed handling of mixed real/int ternary expressions commit | commitdiff | tree
2014-06-24 Clifford WolfMore found_real-related fixes to AstNode::detectSignWid... commit | commitdiff | tree
2014-06-22 Clifford WolfProgress in presentation commit | commitdiff | tree
2014-06-21 Clifford WolfLittle steps in realmath test bench commit | commitdiff | tree
2014-06-21 Clifford Wolffixed signdness detection for expressions with reals commit | commitdiff | tree
2014-06-21 Clifford Wolffixed typo commit | commitdiff | tree
2014-06-21 Clifford WolfProgress in presentation commit | commitdiff | tree
2014-06-19 Clifford WolfDo not create $dffsr cells with no-op resets in proc_dff commit | commitdiff | tree
2014-06-17 Clifford WolfAdded test case for AstNode::MEM2REG_FL_CMPLX_LHS commit | commitdiff | tree
2014-06-17 Clifford WolfAdded AstNode::MEM2REG_FL_CMPLX_LHS commit | commitdiff | tree
2014-06-17 Clifford WolfImproved handling of relational op of real values commit | commitdiff | tree
2014-06-16 Clifford WolfLittle steps in realmath test bench commit | commitdiff | tree
2014-06-16 Clifford WolfImproved ternary support for real values commit | commitdiff | tree
2014-06-16 Clifford WolfUse undef (x/z vs. NaN) rules for real values from... commit | commitdiff | tree
2014-06-16 Clifford WolfFixed parsing of TOK_INTEGER (implies TOK_SIGNED) commit | commitdiff | tree
2014-06-16 Clifford WolfAdded found_real feature to AstNode::detectSignWidth commit | commitdiff | tree
2014-06-15 Clifford WolfAdded more calls to "hierarchy" to README file commit | commitdiff | tree
2014-06-15 Clifford WolfRemoved long running tests from tests/simple/realexpr... commit | commitdiff | tree
2014-06-15 Clifford WolfAdded tests/realmath to "make test" commit | commitdiff | tree
2014-06-15 Clifford WolfImproved AstNode::realAsConst for large numbers commit | commitdiff | tree
2014-06-15 Clifford WolfImproved realmath test bench commit | commitdiff | tree
2014-06-15 Clifford WolfImproved parsing of large integer constants commit | commitdiff | tree
2014-06-15 Clifford WolfImproved AstNode::asReal for large integers commit | commitdiff | tree
2014-06-14 Clifford Wolfimproved realmath test bench commit | commitdiff | tree
2014-06-14 Clifford Wolfimproved (fixed) conversion of real values to bit vectors commit | commitdiff | tree
2014-06-14 Clifford Wolfprogress in realmath test bench commit | commitdiff | tree
2014-06-14 Clifford WolfFixed relational operators for const real expressions commit | commitdiff | tree
2014-06-14 Clifford Wolfadded first draft of real math testcase generator commit | commitdiff | tree
2014-06-14 Clifford WolfProgress in presentation commit | commitdiff | tree
2014-06-14 Clifford WolfAdded %D and %c select commands commit | commitdiff | tree
2014-06-14 Clifford WolfAdded support for math functions commit | commitdiff | tree
2014-06-14 Clifford WolfAdded realexpr.v test case commit | commitdiff | tree
2014-06-14 Clifford WolfAdded handling of real-valued parameters/localparams commit | commitdiff | tree
2014-06-14 Clifford WolfImplemented more real arithmetic commit | commitdiff | tree
2014-06-14 Clifford WolfImplemented basic real arithmetic commit | commitdiff | tree
2014-06-14 Clifford WolfAdded real->int convertion in ast genrtlil commit | commitdiff | tree
2014-06-13 Clifford WolfAdded Verilog lexer and parser support for real values commit | commitdiff | tree
2014-06-12 Clifford WolfAdded read_verilog -sv options, added support for bit... commit | commitdiff | tree
2014-06-08 Clifford WolfNow we are in Yoys 0.3.0+ development commit | commitdiff | tree
2014-06-08 Clifford WolfTagging Yosys 0.3.0 yosys-0.3.0 commit | commitdiff | tree
2014-06-08 Clifford WolfUpdated ABC to 7600ffb9340c commit | commitdiff | tree
2014-06-07 Clifford Wolfadded tests for new verilog features commit | commitdiff | tree
2014-06-07 Clifford Wolffixed cell array handling of positional arguments commit | commitdiff | tree
2014-06-07 Clifford WolfAdd support for cell arrays commit | commitdiff | tree
2014-06-07 Clifford WolfAdded support for repeat stmt in const functions commit | commitdiff | tree
2014-06-06 Clifford Wolffurther improved const function support commit | commitdiff | tree
2014-06-06 Clifford Wolfmade the generate..endgenrate keywords optional commit | commitdiff | tree
2014-06-06 Clifford Wolfimproved const function support commit | commitdiff | tree
2014-06-06 Clifford Wolffix functions with no block (but single statement,... commit | commitdiff | tree
2014-06-06 Clifford WolfAdded tests/simple/repwhile.v commit | commitdiff | tree
2014-06-06 Clifford Wolfimproved ast simplify of const functions commit | commitdiff | tree
2014-06-06 Clifford Wolfadded while and repeat support to verilog parser commit | commitdiff | tree
2014-06-04 Clifford WolfImproved error message for options after front-end... commit | commitdiff | tree
2014-06-03 Clifford Wolfadded tee cmd commit | commitdiff | tree
2014-06-01 Clifford WolfFixed log messages in memory_dff commit | commitdiff | tree
next