yosys.git
2015-05-22 Clifford Wolfpreserve used $-wires with init attribute in opt_clean
2015-05-18 Clifford Wolfbugfix in blif front-end
2015-05-17 Clifford Wolfadded vloghtb test_febe.sh
2015-05-17 Clifford WolfImproved .latch support in BLIF front-end
2015-05-17 Clifford WolfAdded read_blif command
2015-05-17 Clifford WolfGeneralized blifparse API
2015-05-17 Clifford Wolfabc/blifparse files reorganization
2015-05-17 Clifford WolfVerific build fixes
2015-05-13 Clifford WolfAdded .barbuf support to abc BLIF parser
2015-05-11 Clifford Wolfchanged file() to open() in python scripts
2015-05-11 Clifford WolfMerge pull request #63 from wluker/verilog-backend-mem
2015-05-11 luke whittleseyFixed bug in $mem cell verilog code generation.
2015-05-10 Clifford WolfDisabled broken $mem support in verilog backend
2015-05-10 Clifford WolfMerge pull request #62 from wluker/verilog-backend-mem
2015-05-10 luke whittleseyMade changes recommended by Clifford Wolf ...
2015-05-08 luke whittleseyVerilog backend for $mem cells should now be able to...
2015-05-07 luke whittleseyAdded support for $mem cells in the verilog backend.
2015-04-29 Clifford WolfFixed memory_unpack for initialized memories
2015-04-29 Clifford WolfPreserve important attributes in splitnets
2015-04-29 Clifford WolfAdded $eq/$neq -> $logic_not/$reduce_bool optimization
2015-04-27 Clifford Wolfice40_opt bugfix
2015-04-27 Clifford WolfiCE40: SB_CARRY const fold -> unmap SB_LUT
2015-04-27 Clifford WolfAdded simplemap $lut support
2015-04-27 Clifford WolfAdded iCE40 const folding support for SB_CARRY
2015-04-26 Clifford WolfInitialization support for all iCE40 bram modes
2015-04-25 Clifford Wolfinitialized iCE40 brams (mode 0)
2015-04-25 Clifford Wolfimproved iCE40 SB_RAM40_4K simulation model
2015-04-25 Clifford WolfUpdated ABC to hg rev 779de2de1481
2015-04-25 Clifford WolfMore iCE40 bram improvements
2015-04-24 Clifford WolfImproved attributes API and handling of "src" attributes
2015-04-24 Clifford WolfiCE40 bram progress
2015-04-24 Clifford WolfiCE40 bram tests and fixes
2015-04-23 Clifford WolfAdded ice40 bram support
2015-04-22 Clifford WolfFixed memory_share for unconditional write with part...
2015-04-19 Clifford WolfiCE40: Added SB_RAM40_4K{,NR,NW,NRNW}* models
2015-04-19 Clifford WolfVerilog front-end: define `BLACKBOX in -lib mode
2015-04-18 Clifford Wolfadded sync reset to ice40 test_ffs.sh
2015-04-18 Clifford WolfAdded ice40 test_arith
2015-04-18 Clifford WolfAdded ice40 SB_CARRY support
2015-04-18 Clifford Wolfdon't consider blackbox modules in "sat" command
2015-04-18 Clifford WolfImproved handling of init values in opt_rmdff
2015-04-17 Clifford WolfBugfix for $_DFF_?_ in "dff2dffe -direct-match"
2015-04-17 Clifford WolfAdded mapping of synchronous set/reset to iCE40 flow
2015-04-16 Clifford WolfImproved "maccmap" help message
2015-04-16 Clifford WolfA "#" does start a comment, not a label.
2015-04-16 Clifford WolfChanged ice40 ICESTORM_CARRYCONST port name
2015-04-16 Clifford WolfFixed "dff2dffe -direct-match"
2015-04-16 Clifford WolfAdded simple ice40 dff tests
2015-04-16 Clifford Wolfimproved ice40 dff cell mapping
2015-04-16 Clifford WolfAdded "dff2dffe -direct-match"
2015-04-14 Clifford Wolfuse "hierarchy -auto-top" in synth_ice40
2015-04-14 Clifford Wolfmore cells in ice40 cell library
2015-04-13 Clifford WolfAdded "splice -wires"
2015-04-13 Clifford WolfAdded handling of bool-output cells to "wreduce"
2015-04-09 Clifford WolfImproved xilinx "bram1" test
2015-04-09 Clifford WolfAdded memory_bram "make_outreg" feature
2015-04-09 Clifford WolfAdded back-end auto-detect for .edif and .json
2015-04-09 Clifford WolfMinor fixes in handling of "init" attribute
2015-04-09 Clifford WolfXilinx DRAMS: RAM64X1D, RAM128X1D
2015-04-09 Clifford WolfFixed const2big performance bug
2015-04-09 Clifford Wolftechmap code cleanup
2015-04-09 Clifford WolfTowards DRAM support in Xilinx flow
2015-04-08 Clifford WolfAdded support for "file names with blanks"
2015-04-08 Clifford WolfRemoved "techmap -share_map" (use "-map +/filename...
2015-04-07 Clifford WolfAdded %M and %C select operators
2015-04-07 Clifford WolfAdded "pmuxtree" command
2015-04-07 Clifford WolfAdded "chparam -list"
2015-04-07 Clifford WolfAdded decoder generation to "muxcover"
2015-04-07 Clifford WolfAdded hashlib support for std::tuple<>
2015-04-07 Clifford WolfAdded "muxcover" command
2015-04-07 Clifford WolfAdded pool<K>::pop()
2015-04-07 Clifford Wolftypo fix
2015-04-07 Clifford WolfAdded "chparam" command
2015-04-06 Clifford WolfAdded support for initialized xilinx brams
2015-04-06 Clifford WolfAdded support for initialized brams
2015-04-06 Clifford WolfAdded Xilinx test case for initialized brams
2015-04-06 Clifford WolfAdded Xilinx bram black-box modules
2015-04-05 Clifford WolfAdded "port_directions" to write_json output
2015-04-05 Clifford WolfAvoid parameter values with size 0 ($mem cells)
2015-04-05 Clifford Wolfmake all vector-size related integer params in $mem...
2015-04-05 Clifford WolfAdded $_MUX4_, $_MUX8_, and $_MUX16_ cell types
2015-04-04 Clifford WolfAdded "dffinit", Support for initialized Xilinx DFF
2015-04-04 Clifford WolfAdded "init" attribute support to verilog backend
2015-04-04 Clifford Wolfappnote 012 fix
2015-04-04 Clifford WolfAppnote 012
2015-04-04 Clifford WolfUpdated ABC to 51705b168d7a
2015-04-04 Clifford WolfMerge pull request #55 from ahmedirfan1983/master
2015-04-03 Ahmed IrfanUpdate README
2015-04-03 Ahmed IrfanDelete btor.ys
2015-04-03 Ahmed IrfanUpdate README
2015-04-03 Ahmed Irfanseparated memory next from write cell
2015-04-03 Ahmed IrfanMerge branch 'master' of https://github.com/cliffordwol...
2015-04-03 Ahmed IrfanMerge branch 'btor' of https://github.com/ahmedirfan198...
2015-04-03 Ahmed Irfanappnote for verilog to btor
2015-03-29 Clifford Wolfdocumentation improvements
2015-03-25 Clifford WolfIgnore celldefine directive in verilog front-end
2015-03-25 Clifford WolfFixes in cmos_cells.v
2015-03-22 Clifford WolfFixed detection of absolute paths in ABC for win32
2015-03-22 Clifford WolfAdded blif reference to appnote 010
2015-03-20 Clifford WolfMerge branch 'master' of github.com:cliffordwolf/yosys
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