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yosys.git
2019-02-08
Eddie Hung
Copy abc.cc to abc9.cc
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2019-02-08
Eddie Hung
addDff -> addDffGate as per @daveshah1
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2019-02-08
Eddie Hung
Fix tabulation
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2019-02-08
Eddie Hung
-module_name arg to go before -clk_name
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2019-02-08
Eddie Hung
Support and differentiate between ASCII and binary...
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2019-02-08
Eddie Hung
Add missing "[options]" to read_blif help
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2019-02-08
Eddie Hung
Allow module name to be determined by argument too
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2019-02-08
Eddie Hung
Refactor into AigerReader class
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2019-02-08
Eddie Hung
Parse binary AIG files
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2019-02-08
Eddie Hung
Add binary AIGs converted from AAG
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2019-02-08
Eddie Hung
Refactor to parse_aiger_header()
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2019-02-08
Eddie Hung
Add comment
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2019-02-08
Eddie Hung
Handle reset logic in latches
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2019-02-08
Eddie Hung
Change literal vars from int to unsigned
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2019-02-08
Eddie Hung
Create clk outside of latch loop
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2019-02-08
Eddie Hung
Handle latch symbols too
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2019-02-08
Eddie Hung
Remove return after log_error
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2019-02-08
Eddie Hung
Add support for symbol tables
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2019-02-08
Eddie Hung
Stub for binary AIGER
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2019-02-06
Eddie Hung
Refactor
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2019-02-06
Eddie Hung
Merge branch 'dff_init' of https://github.com/eddiehung...
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2019-02-06
Eddie Hung
Revert most of autotest.sh; for non *.v use Yosys to...
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2019-02-06
Eddie Hung
Refactor
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2019-02-06
Eddie Hung
write_verilog to cope with init attr on q when -noexpr
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2019-02-06
Eddie Hung
Add INIT parameter to all ff/latch cells
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2019-02-06
Eddie Hung
Add tests for simple cases using defparam
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2019-02-06
Eddie Hung
Add -B option to autotest.sh to append to backend_opts
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2019-02-06
Eddie Hung
Extend testcase
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2019-02-06
Eddie Hung
Add testcase
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2019-02-06
Eddie Hung
Rename ASCII tests
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2019-02-06
Eddie Hung
WIP
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2019-02-06
Clifford Wolf
Add missing blackslash-to-slash convertion to smtio...
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2019-02-05
Eddie Hung
Add tests
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2019-01-27
Clifford Wolf
Merge pull request #798 from mmicko/master
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2019-01-27
Clifford Wolf
Merge pull request #800 from whitequark/write_verilog_t...
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2019-01-27
Clifford Wolf
Merge branch 'whitequark-write_verilog_keyword'
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2019-01-27
Clifford Wolf
Remove asicworld tests for (unsupported) switch-level...
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2019-01-27
whitequark
write_verilog: write $tribuf cell as ternary.
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2019-01-27
whitequark
write_verilog: escape names that match SystemVerilog...
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2019-01-25
David Shah
Merge pull request #796 from whitequark/proc_clean_typo
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2019-01-25
Miodrag Milanovic
Fixed Anlogic simulation model
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2019-01-23
whitequark
proc_clean: fix critical typo.
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2019-01-19
Clifford Wolf
Merge pull request #793 from whitequark/proc_clean_fix_...
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2019-01-18
whitequark
proc_clean: fix fully def check to consider compare...
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2019-01-17
Clifford Wolf
Cleanups in igloo2 example design
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2019-01-17
Clifford Wolf
Add SF2 IO buffer insertion
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2019-01-17
Clifford Wolf
Improve Igloo2 example
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2019-01-17
Clifford Wolf
Add "synth_sf2 -vlog", fix "synth_sf2 -edif"
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2019-01-17
Clifford Wolf
Add "write_edif -gndvccy"
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2019-01-15
Clifford Wolf
Add optional nullstr argument to log_id()
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2019-01-15
Clifford Wolf
Fix handling of $shiftx in Verilog back-end
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2019-01-15
Clifford Wolf
Merge pull request #788 from whitequark/master
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2019-01-15
Clifford Wolf
Merge pull request #787 from whitequark/flowmap_relax
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2019-01-14
whitequark
manual: document some gates.
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2019-01-14
whitequark
manual: explain $tribuf cell.
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2019-01-08
Clifford Wolf
Improve igloo2 example
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2019-01-08
whitequark
flowmap: clean up terminology.
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2019-01-08
whitequark
flowmap: implement depth relaxation.
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2019-01-07
Clifford Wolf
Fix typo in manual
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2019-01-07
Clifford Wolf
Bugfix in $memrd sharing
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2019-01-07
Clifford Wolf
Merge pull request #782 from whitequark/flowmap_dfs
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2019-01-07
Clifford Wolf
Switch "bugpoint" from system() to run_command()
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2019-01-07
Clifford Wolf
Merge pull request #783 from whitequark/bugpoint
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2019-01-07
whitequark
bugpoint: new pass.
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2019-01-06
whitequark
flowmap: construct a max-volume max-flow min-cut, not...
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2019-01-06
Clifford Wolf
Merge pull request #780 from phire/rename_from_wire
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2019-01-06
Scott Mansell
Rename cells based on the wires they drive.
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2019-01-05
Clifford Wolf
Add skeleton Yosys-Libero igloo2 example project
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2019-01-05
Clifford Wolf
Bugfix in Verilog string handling
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2019-01-04
whitequark
flowmap: add -minlut option, to allow postprocessing...
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2019-01-04
Clifford Wolf
Merge pull request #777 from mmicko/achronix_cell_sim_fix
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2019-01-04
Miodrag Milanovic
Fix cells_sim.v for Achronix FPGA
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2019-01-04
Clifford Wolf
Remove -m32 Verific eval lib build instructions
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2019-01-04
Clifford Wolf
Merge pull request #776 from mmicko/unify_noflatten
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2019-01-04
Clifford Wolf
Update Verific default path
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2019-01-04
whitequark
flowmap: cleanup for clarity. NFCI.
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2019-01-04
Miodrag Milanovic
Unify usage of noflatten among architectures
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2019-01-04
whitequark
flowmap: improve debug graph output. NFC.
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2019-01-04
whitequark
flowmap: add link to longer version of paper. NFC.
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2019-01-03
Clifford Wolf
Merge pull request #775 from whitequark/opt_flowmap
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2019-01-03
whitequark
flowmap: new techmap pass.
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2019-01-02
Clifford Wolf
Merge pull request #770 from whitequark/opt_expr_cmp
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2019-01-02
whitequark
opt_expr: improve simplification of comparisons with...
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2019-01-02
Clifford Wolf
Merge pull request #755 from Icenowy/anlogic-dram-init
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2019-01-02
Clifford Wolf
Merge branch 'master' of github.com:YosysHQ/yosys
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2019-01-02
Clifford Wolf
Merge pull request #750 from Icenowy/anlogic-ff-init
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2019-01-02
Clifford Wolf
Merge pull request #773 from whitequark/opt_lut_elim_fixes
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2019-01-02
Clifford Wolf
Merge pull request #772 from whitequark/synth_lut
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2019-01-02
Clifford Wolf
Merge pull request #771 from whitequark/techmap_cmp2lut
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2019-01-02
Clifford Wolf
Improve VerificImporter support for writes to asymmetri...
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2019-01-02
Clifford Wolf
Fix VerificImporter asymmetric memories error message
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2019-01-02
Clifford Wolf
Merge pull request #769 from whitequark/typos
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2019-01-02
whitequark
Fix typographical and grammatical errors and inconsiste...
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2019-01-02
whitequark
opt_lut: reflect changes in sigmap.
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2019-01-02
whitequark
opt_lut: use a worklist, and revisit cells affected...
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2019-01-02
whitequark
opt_lut: count eliminated cells, and set opt.did_someth...
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2019-01-02
whitequark
synth_ice40: use 4-LUT coarse synthesis mode.
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2019-01-02
whitequark
synth: add k-LUT mode.
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2019-01-02
whitequark
synth: improve script documentation. NFC.
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2019-01-02
whitequark
cmp2lut: new techmap pass.
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