gem5.git
2019-05-17 Jason Lowe... configs: Generalize FileSystemConfig for non se.py
2019-05-17 Ciro Santilliarch-arm: implement VMINNM and VMAXNM scalar version
2019-05-17 Ciro Santilliarch-arm: implement VMINNM and VMAXNM SIMD version
2019-05-17 Ciro Santilliarch-arm: rename operands to match spec in isa/formats...
2019-05-14 Tiago Muckmem-ruby: MOESI_CMP_dir cleanup
2019-05-14 Tiago Muckmem-ruby: Cache latencies for MOESI_CMP_dir
2019-05-14 Tiago Muckmem-ruby: Hit latencies defined by the controllers
2019-05-14 Tiago Muckmem-ruby: Do not change blocked msg enqueue info
2019-05-14 Tiago Muckmem-ruby: Unique ranks for MOESI_CMP_dir in ports
2019-05-14 Tiago Muckmem-ruby: Change MOESI_CMP_Dir L2 addressing
2019-05-14 Tiago Muckmem-ruby: Fix MOESI_CMP_dir debug msg
2019-05-14 Tiago Muckmem-ruby: Prevent response stalls on MOESI_CMP_directory
2019-05-14 Javier Buenoarch-arm: Do not check MustBeOne flag for TLB requests...
2019-05-14 Javier Buenoconfigs: Fix duplicate branchPred reference in Simulati...
2019-05-14 Giacomo TravagliniRevert "cpu: fix how a thread starts up in MinorCPU"
2019-05-14 Giacomo TravagliniRevert "cpu: stop scheduling suspended threads in MinorCPU"
2019-05-14 Giacomo TravagliniRevert "cpu: fix branching when thread is suspended...
2019-05-14 Danielmem-cache: Use SatCounter for prefetchers
2019-05-14 Danielbase: Add operators to SatCounter
2019-05-14 Danielbase: Add GTest to SatCounter
2019-05-14 Danielbase: Move SatCounter to base directory
2019-05-14 Danielcpu: Revamp saturating counters
2019-05-13 Jairo Balartconfig: add an option to list and select indirect branc...
2019-05-13 Jairo Balartcpu: Make the indirect predictor into a SimObject
2019-05-12 Daniel R. Carvalhomem-ruby: Replace string parameter in MultiBitSelBloomF...
2019-05-11 Giacomo Gabrielliarch-arm: Add initial support for SVE contiguous loads...
2019-05-11 Giacomo Gabriellicpu,mem: Add support for partial loads/stores and wide...
2019-05-11 Giacomo Gabriellicpu: Add a memory access predicate
2019-05-10 Brandon Potterconfig, sim-se: bugfix for 54c77aa0
2019-05-09 Daniel R. Carvalhoconfigs: Fix FileSystemConfig import
2019-05-09 Daniel R. Carvalhotests: Fix import scope of test
2019-05-09 Tiago Muckmem-ruby: Fix MOESI_CMP_directory blocked line handling
2019-05-08 Daniel R. Carvalhomem-cache: Remove writebacks packet list
2019-05-08 Daniel R. Carvalhomem-cache: Handle data expansion
2019-05-08 Daniel R. Carvalhomem-cache: Add co-allocation function to compressed...
2019-05-08 Daniel R. Carvalhomem-cache: Add compression and decompression calls
2019-05-08 Daniel R. Carvalhomem-cache: Create BDI Compressor
2019-05-08 Daniel R. Carvalhomem-cache: Add compression stats
2019-05-08 Daniel R. Carvalhomem-cache: Create cache compressor
2019-05-08 Daniel R. Carvalhomem-cache: Add block size to findVictim
2019-05-08 Daniel R. Carvalhomem-cache: Add compression data to CompressionBlk
2019-05-08 Daniel R. Carvalhomem-cache: Create CacheComp debug flag
2019-05-08 Daniel R. Carvalhomem-cache: Stub compression framework
2019-05-07 Gabor Dozsax86: Mark translation as delayed in case of a hw page...
2019-05-06 Andrea Mondellisim-se: correct statfs inclusion on !linux host
2019-05-04 Alec Roelkearch-riscv: Implement MHARTID CSR
2019-05-03 Joe Grosssim-se: fix a few bugs/warns from GCC 6
2019-05-03 Brandon Pottersim-se: add eventfd system call
2019-05-03 Nikos Nikolerismem-cache: Mark block as dirty after a SWPrefetchEXResp
2019-05-03 Avishai Tvilaarch-riscv,isa: Fix for compressed jump (c_j) imm
2019-05-03 Giacomo Travaglinidev: StreamID generation in DMA device
2019-05-02 Gabe Blacktests: There is no architecture called "timing".
2019-05-02 Giacomo Travaglinidev-arm: Store a PhysProxy port in Gicv3Redist
2019-05-02 Giacomo Travaglinidev-arm: Add named variable for GICD_TYPER.IDBits
2019-05-02 Giacomo Travaglinidev-arm: Read correct version of ICC_BPR register
2019-05-02 Giacomo Travaglinidev-arm: Get a Gicv3Redistributor ptr from phys address
2019-05-02 Giacomo Travaglinidev-arm: Add several LPI methods in Gicv3Redistributor
2019-05-02 Giacomo Travaglinidev-arm: Take LPIs into account when interacting with...
2019-05-02 Giacomo Travaglinidev-arm: Fix GICv3 LPIs priority value
2019-05-02 Giacomo Travaglinidev-arm: Disable LPI Configuration Table caching
2019-05-02 Giacomo Travaglinidev-arm: Check EnableLPIs before checking for pending...
2019-05-02 Giacomo Travaglinidev-arm: GICv3 LPI tables are using physical addresses
2019-05-02 Giacomo Travaglinidev-arm: Fix GICv3 LPI loop
2019-05-02 Giacomo Travaglinidev-arm: Fix Bitwise operation in GICv3
2019-05-02 Daniel R. Carvalhotests: Add missing kernels to system creation
2019-04-30 Gabe Blackarch: Stop using TheISA within the ISAs.
2019-04-30 Gabe Blackx86: Get rid of some unnecessary TheISA-es in x86.
2019-04-30 Gabe Blacksparc: Move translation constants from isa_traits.hh...
2019-04-30 Gabe Blacksparc: Move the interrupt types out of isa_traits.hh...
2019-04-30 Gabe Blackarch: Remove the mt.hh switching header.
2019-04-30 Gabe Blackcpu: alpha: Delete all occurrances of the simPalCheck...
2019-04-30 Gabe Blackalpha: Implement simPalCheck within the ISA description.
2019-04-30 Gabe Blackcpu: Remove hwrei from the generic interfaces.
2019-04-30 Alexandru Dutusim-se: use DPRINTF_SYSCALL for ioctl/wait4
2019-04-30 Brandon Pottersim-se: bugfix for 54c77aa055e
2019-04-30 Gabe Blackarch: cpu: Track kernel stats using the base ISA agnost...
2019-04-30 Gabe Blackalpha: Implement HWREI in the ISA.
2019-04-30 Gabe Blackalpha: Add some control registers to the ISA operands...
2019-04-30 Brandon Pottersim-se: add socket ioctls
2019-04-30 Gabe Blacksystemc: Add a distinct async_request_update mechanism.
2019-04-29 Gabe Blackcpu: Get rid of the (read|set)RegOtherThread methods.
2019-04-29 Gabe Blackmips: Implement readRegOtherThread and setRegOtherThrea...
2019-04-29 Gabe Blackcpu: Include debug flags regardless of whether the...
2019-04-29 Steve Reinhardtsim-se: create Proc out files in out dir
2019-04-29 Giacomo Travagliniarch-arm: Faults DebugFlag now printing inst opcode...
2019-04-29 Giacomo Travagliniarch-arm: Report real instruction encoding when Undefined
2019-04-28 Gabe Blackarch, sim: Simplify the AuxVector type.
2019-04-28 Gabe Blackmem: Remove the ISA specialized versions of port proxy...
2019-04-28 Gabe Blackmem: Minimize the use of MemObject.
2019-04-27 Gabe Blackpython: Get rid of the VectorPort constructor.
2019-04-27 Gabe Blackpython: Replace the Master/Slave Ports with Request...
2019-04-26 Giacomo Travagliniarch-arm: updateMiscReg not setting isHyp in aarch64
2019-04-26 Gabe Blackarm: Factor some repetition out of the ProcessInfo...
2019-04-25 Gabe Blackarm: Fix some style issues in stacktrace.cc.
2019-04-25 Gabe Blackx86: Refactor the ProcessInfo constructor.
2019-04-25 David Hasheconfigs: faux-filesystem fix w/ ruby in se mode
2019-04-25 Gabe Blackx86: Fix some style issues in stacktrace.cc.
2019-04-25 David Hashesim-se: add a faux-filesystem
2019-04-25 Giacomo Travagliniarch-arm: Remove un-needed hyp flag in TLBI operations
2019-04-25 Giacomo Travagliniarch-arm: Correct target EL field in TLBI operations
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