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yosys.git
2014-07-30 Clifford WolfAdded CodingStyle document commit | commitdiff | tree
2014-07-30 Clifford WolfAdded "kernel/yosys.h" and "kernel/yosys.cc" commit | commitdiff | tree
2014-07-29 Clifford WolfAdded "test_cell" command commit | commitdiff | tree
2014-07-29 Clifford WolfRenamed "write_autotest" to "test_autotb" and moved... commit | commitdiff | tree
2014-07-29 Clifford WolfFixed Verilog pre-processor for files with no trailing... commit | commitdiff | tree
2014-07-29 Clifford WolfBugfix in simlib.v for iverilog commit | commitdiff | tree
2014-07-29 Clifford WolfAllow "hierarchy -generate" for $__ cells commit | commitdiff | tree
2014-07-29 Clifford WolfAdded "techmap -map %{design-name}" commit | commitdiff | tree
2014-07-29 Clifford WolfAdded $shift and $shiftx cell types (needed for correct... commit | commitdiff | tree
2014-07-28 Clifford WolfRemoved left over debug code commit | commitdiff | tree
2014-07-28 Clifford WolfFixed part selects of parameters commit | commitdiff | tree
2014-07-28 Clifford WolfSet results of out-of-bounds static bit/part select... commit | commitdiff | tree
2014-07-28 Clifford WolfFixed RTLIL code generator for part select of parameter commit | commitdiff | tree
2014-07-28 Clifford WolfFixed width detection for part selects commit | commitdiff | tree
2014-07-28 Clifford WolfAdded support for "upto" wires to Verilog front- and... commit | commitdiff | tree
2014-07-28 Clifford WolfAdded wire->upto flag for signals such as "wire [0... commit | commitdiff | tree
2014-07-28 Clifford WolfUsing log_assert() instead of assert() commit | commitdiff | tree
2014-07-28 Clifford WolfAdded std::initializer_list<> constructor to SigSpec commit | commitdiff | tree
2014-07-28 Clifford WolfAdded cover() to all SigSpec constructors commit | commitdiff | tree
2014-07-28 Clifford WolfFixed signdness detection of expressions with bit-... commit | commitdiff | tree
2014-07-28 Clifford WolfImprovements in tests/vloghtb commit | commitdiff | tree
2014-07-27 Clifford WolfAdded techmap -extern commit | commitdiff | tree
2014-07-27 Clifford WolfAdded proper Design->addModule interface commit | commitdiff | tree
2014-07-27 Clifford WolfAdded topological sorting to techmap commit | commitdiff | tree
2014-07-27 Clifford WolfAdded SigPool::check(bit) commit | commitdiff | tree
2014-07-27 Clifford WolfSmall improvements in PerformanceTimer API commit | commitdiff | tree
2014-07-27 Clifford WolfFixed bug in opt_clean commit | commitdiff | tree
2014-07-27 Clifford WolfImproved performance of opt_const on large modules commit | commitdiff | tree
2014-07-27 Clifford WolfAdded RTLIL::SigSpec::remove_const() handling of packed... commit | commitdiff | tree
2014-07-27 Clifford WolfAdded RTLIL::SigSpecConstIterator commit | commitdiff | tree
2014-07-27 Clifford WolfFixed a bug in opt_clean and some RTLIL API usage cleanups commit | commitdiff | tree
2014-07-27 Clifford WolfAdded log_cmd_error_expection commit | commitdiff | tree
2014-07-27 Clifford WolfFixed verific bindings for new RTLIL api commit | commitdiff | tree
2014-07-27 Clifford WolfFixed ilang parser for new RTLIL API commit | commitdiff | tree
2014-07-27 Clifford WolfUsing new obj iterator API in a few places commit | commitdiff | tree
2014-07-27 Clifford WolfAdded RTLIL::Module::wire(id) and cell(id) lookup functions commit | commitdiff | tree
2014-07-27 Clifford WolfAdded RTLIL::Design::modules() commit | commitdiff | tree
2014-07-27 Clifford WolfRefactoring: Renamed RTLIL::Design::modules to modules_ commit | commitdiff | tree
2014-07-27 Clifford WolfAdded conversion from ObjRange to std::vector and std... commit | commitdiff | tree
2014-07-27 Clifford WolfAdded RTLIL::ObjIterator and RTLIL::ObjRange commit | commitdiff | tree
2014-07-27 Clifford WolfUsing std::move() in SigSpec move constructor commit | commitdiff | tree
2014-07-27 Clifford WolfAdded RTLIL::SigSpec move constructor and move assignme... commit | commitdiff | tree
2014-07-27 Clifford WolfMostly cosmetic changes to rtlil.h commit | commitdiff | tree
2014-07-26 Clifford WolfRefactoring: Renamed RTLIL::Module::cells to cells_ commit | commitdiff | tree
2014-07-26 Clifford WolfRefactoring: Renamed RTLIL::Module::wires to wires_ commit | commitdiff | tree
2014-07-26 Clifford WolfNew message for completion of build commit | commitdiff | tree
2014-07-26 Clifford WolfChanged more code to the new RTLIL::Wire constructors commit | commitdiff | tree
2014-07-26 Clifford WolfChanged a lot of code to the new RTLIL::Wire constructors commit | commitdiff | tree
2014-07-26 Clifford WolfAdded tests/various/.gitignore commit | commitdiff | tree
2014-07-26 Clifford WolfAdded tests/various/submod_extract.ys commit | commitdiff | tree
2014-07-26 Clifford WolfAdded support for here documents commit | commitdiff | tree
2014-07-26 Clifford WolfMore RTLIL::Cell API usage cleanups commit | commitdiff | tree
2014-07-26 Clifford WolfAdded RTLIL::Cell::has(portname) commit | commitdiff | tree
2014-07-26 Clifford WolfMerge automatic and manual code changes for new cell... commit | commitdiff | tree
2014-07-26 Clifford WolfManual fixes for new cell connections API commit | commitdiff | tree
2014-07-26 Clifford WolfChanged users of cell->connections_ to the new API... commit | commitdiff | tree
2014-07-26 Clifford WolfAdded some missing "const" in rtlil.h commit | commitdiff | tree
2014-07-26 Clifford WolfAdded RTLIL::Module::connections() commit | commitdiff | tree
2014-07-26 Clifford WolfAdded RTLIL::Module::connect(const RTLIL::SigSig&) commit | commitdiff | tree
2014-07-26 Clifford WolfUse "wget -N" in tests/vloghtb/run-test.sh commit | commitdiff | tree
2014-07-26 Clifford WolfAdded "passed" message to make test targets commit | commitdiff | tree
2014-07-26 Clifford WolfAutomatically pack SigSpec on copy/assign commit | commitdiff | tree
2014-07-26 Clifford WolfAdded new RTLIL::Cell port access methods commit | commitdiff | tree
2014-07-26 Clifford WolfRenamed RTLIL::{Module,Cell}::connections to connections_ commit | commitdiff | tree
2014-07-26 Clifford WolfCosmetic fixes for "make abc" commit | commitdiff | tree
2014-07-26 Clifford WolfAdded "Checklist for adding internal cell types" commit | commitdiff | tree
2014-07-25 Clifford WolfAdded copy-constructor-like module->addCell(name, other... commit | commitdiff | tree
2014-07-25 Clifford WolfUse only module->addCell() and module->remove() to... commit | commitdiff | tree
2014-07-25 Clifford WolfVarious RTLIL::SigSpec related code cleanups commit | commitdiff | tree
2014-07-25 Clifford WolfAdded RTLIL::SigSpec is_chunk()/as_chunk() API commit | commitdiff | tree
2014-07-25 Clifford WolfAdded "make vgtest" commit | commitdiff | tree
2014-07-25 Clifford WolfFixed two memory leaks in ast simplify commit | commitdiff | tree
2014-07-25 Clifford WolfRenamed some of the test cases in tests/simple to avoid... commit | commitdiff | tree
2014-07-25 Clifford WolfFixed memory corruption in "opt_reduce" pass commit | commitdiff | tree
2014-07-25 Clifford WolfDisabled cover() for non-linux builds commit | commitdiff | tree
2014-07-25 Clifford WolfAdded more stuff to checklist commit | commitdiff | tree
2014-07-25 Clifford WolfUpdated verific build/test instructions commit | commitdiff | tree
2014-07-25 Clifford WolfImprovements in "cover" command commit | commitdiff | tree
2014-07-25 Clifford WolfRemoved Minisat dependency on zlib commit | commitdiff | tree
2014-07-25 Clifford WolfAdded more stuff to the checklist commit | commitdiff | tree
2014-07-25 Clifford WolfFixed typo in cover id commit | commitdiff | tree
2014-07-25 Clifford WolfAdded "make clean-abc" commit | commitdiff | tree
2014-07-25 Clifford WolfFurther improved "make" prettiness commit | commitdiff | tree
2014-07-24 Clifford WolfReplaced more old SigChunk programming patterns commit | commitdiff | tree
2014-07-24 Clifford WolfUpdated ABC to hg id "b1e63d18768d" commit | commitdiff | tree
2014-07-24 Clifford WolfAdded cover() calls to opt_const commit | commitdiff | tree
2014-07-24 Clifford WolfAdded cover_list() API commit | commitdiff | tree
2014-07-24 Clifford WolfAdded "make SMALL=1" commit | commitdiff | tree
2014-07-24 Clifford WolfNow "make PRETTY=1" is the default setting commit | commitdiff | tree
2014-07-24 Clifford WolfAdded percentage display to "make PRETTY=1" commit | commitdiff | tree
2014-07-24 Clifford WolfAdded "make PRETTY=1" commit | commitdiff | tree
2014-07-24 Clifford WolfAdded "cover" command commit | commitdiff | tree
2014-07-24 Clifford WolfSome improvements in SigSpec packing/unpacking and... commit | commitdiff | tree
2014-07-24 Clifford WolfNow using a dedicated ELF section for all coverage... commit | commitdiff | tree
2014-07-24 Clifford WolfSmall changes regarding cover() and check() in SigSpec commit | commitdiff | tree
2014-07-24 Clifford WolfRenamed RELEASE_CHECKLIST -> CHECKLIST commit | commitdiff | tree
2014-07-24 Clifford WolfAdded support for YOSYS_COVER_FILE env variable commit | commitdiff | tree
2014-07-24 Clifford WolfAdded cover() calls to RTLIL::SigSpec methods commit | commitdiff | tree
2014-07-24 Clifford WolfAdded support for YOSYS_COVER_DIR env variable commit | commitdiff | tree
2014-07-24 Clifford WolfAdded cover() API commit | commitdiff | tree
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