| 2017-12-09 |
Clifford Wolf | Add Verific OPER_SVA_STABLE support |
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| 2017-12-09 |
Clifford Wolf | Refactoring Verific SVA rewriter |
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| 2017-12-09 |
Clifford Wolf | Merge pull request #467 from mithro/patch-1 |
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| 2017-12-09 |
Tim Ansell | Fix spelling in -vpr help for synth_ice40 |
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| 2017-12-03 |
Clifford Wolf | Use "hg ... --insecure" for cloning/pulling ABC |
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| 2017-12-02 |
Clifford Wolf | Update ABC to hg rev 31fc97b0aeed |
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| 2017-12-02 |
Clifford Wolf | Fix error handling for nested always/initial |
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| 2017-11-28 |
Clifford Wolf | Merge pull request #462 from daveshah1/up5k |
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| 2017-11-28 |
David Shah | Add remaining UltraPlus cells to ice40 techlib |
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| 2017-11-27 |
Clifford Wolf | Fixed "yosys-smtbmc -g" handling of no solution |
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| 2017-11-26 |
Clifford Wolf | Merge pull request #460 from mithro/g3-fixes |
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| 2017-11-26 |
Clifford Wolf | Merge pull request #461 from mithro/travis-rework |
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| 2017-11-26 |
Tim 'mithro... | travis: Print branches before fetching, try both locations. |
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| 2017-11-26 |
Tim 'mithro... | minisat: Make update script executable. |
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| 2017-11-26 |
Tim 'mithro... | minisat: Only define __STDC_XXX_MACROS if not already... |
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| 2017-11-26 |
Tim 'mithro... | minisat: Remove template with gzFile specialization. |
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| 2017-11-26 |
Tim 'mithro... | subcircuit: Class with virtual methods should have... |
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| 2017-11-24 |
Clifford Wolf | Merge pull request #446 from mithro/travis-rework |
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| 2017-11-24 |
Tim 'mithro... | travis: Use the cache. |
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| 2017-11-24 |
Tim 'mithro... | travis: Adding gcc-4.8 and gcc-6 on Linux. |
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| 2017-11-24 |
Tim 'mithro... | travis: Reworking travis setup. |
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| 2017-11-23 |
Clifford Wolf | Merge branch 'master' of github.com:cliffordwolf/yosys |
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| 2017-11-23 |
Clifford Wolf | Add Verilog "automatic" keyword (ignored in synthesis) |
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| 2017-11-18 |
Clifford Wolf | Merge pull request #455 from daveshah1/up5k |
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| 2017-11-18 |
David Shah | Remove unnecessary keep attributes |
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| 2017-11-18 |
Clifford Wolf | Accept real-valued delay values |
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| 2017-11-18 |
Clifford Wolf | Merge pull request #452 from cr1901/master |
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| 2017-11-18 |
Clifford Wolf | Merge pull request #453 from dh73/master |
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| 2017-11-17 |
David Shah | Merge branch 'master' into up5k |
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| 2017-11-16 |
Clifford Wolf | Add "synth_ice40 -vpr" |
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| 2017-11-16 |
David Shah | Add some UltraPlus cells to ice40 techlib |
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| 2017-11-15 |
dh73 | Fixed the -vout flag to -vqm in examples/intel directory |
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| 2017-11-14 |
William D.... | Accommodate Windows-style paths during include-file... |
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| 2017-11-09 |
dh73 | Initial Cyclone 10 support |
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| 2017-11-09 |
dh73 | Merge https://github.com/cliffordwolf/yosys |
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| 2017-11-09 |
dh73 | Organizing Speedster file names |
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| 2017-11-08 |
Clifford Wolf | Add support for editline as replacement for readline |
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| 2017-10-31 |
Clifford Wolf | Add "ltp" command |
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| 2017-10-29 |
Clifford Wolf | Fix SMT2 handling of initstate in sub-modules |
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| 2017-10-26 |
Clifford Wolf | Fix memory corruption bug in opt_rmdff |
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| 2017-10-26 |
Clifford Wolf | Fix typo in opt_clean log message |
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| 2017-10-25 |
Clifford Wolf | Improve smtio performance by using reader thread, not... |
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| 2017-10-25 |
Clifford Wolf | Use separate writer thread for talking to SMT solver... |
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| 2017-10-25 |
Clifford Wolf | Improve p_* functions in smtio.py |
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| 2017-10-25 |
Clifford Wolf | Disable OSX in .travis.yml |
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| 2017-10-25 |
Clifford Wolf | Add ENABLE_DEBUG config flag |
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| 2017-10-25 |
Clifford Wolf | Update ABC to hg rev f6838749f234 |
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| 2017-10-25 |
Clifford Wolf | Remove vhdl2verilog |
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| 2017-10-25 |
Clifford Wolf | Capsulate smt-solver read/write in separate functions |
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| 2017-10-25 |
Clifford Wolf | Fix a bug in yosys-smtbmc in ROM handling |
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| 2017-10-20 |
Clifford Wolf | Remove PSL example from tests/sva/ |
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| 2017-10-20 |
Clifford Wolf | Remove all PSL support code from verific.cc |
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| 2017-10-20 |
Clifford Wolf | Merge pull request #437 from mithro/master |
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| 2017-10-20 |
Tim 'mithro... | Adding COPYING file with license information. |
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| 2017-10-14 |
Clifford Wolf | Revert 90be0d8 as it causes endless loops for some... |
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| 2017-10-13 |
Clifford Wolf | Add "verific -vlog-libdir" |
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| 2017-10-13 |
Clifford Wolf | Add "verific -vlog-incdir" and "verific -vlog-define" |
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| 2017-10-13 |
Clifford Wolf | Update Verific README |
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| 2017-10-12 |
Clifford Wolf | Merge pull request #434 from Kmanfi/vector_fix |
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| 2017-10-12 |
Kaj Tuomi | Fix input vector for reduce cells. |
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| 2017-10-12 |
Clifford Wolf | Add Verific fairness/liveness support |
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| 2017-10-11 |
Clifford Wolf | Update ABC to hg rev 6283c5d99b06 |
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| 2017-10-10 |
Clifford Wolf | Merge branch 'master' of github.com:cliffordwolf/yosys |
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| 2017-10-10 |
Clifford Wolf | Start work on pre-processor for Verific SVA properties |
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| 2017-10-10 |
Clifford Wolf | Rewrite ABC output to include proper net names in timin... |
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| 2017-10-10 |
Clifford Wolf | Add timing constraints to osu035 example |
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| 2017-10-10 |
Clifford Wolf | Remove some dead code |
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| 2017-10-10 |
Clifford Wolf | Allow $past, $stable, $rose, $fell in $global_clock... |
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| 2017-10-07 |
Clifford Wolf | Add $shiftx support to verilog front-end |
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| 2017-10-06 |
Clifford Wolf | Update ABC to hg rev 0fc1803a77c0 |
commit | commitdiff | tree |
| 2017-10-05 |
Larry Doolittle | Clean whitespace and permissions in techlibs/intel |
commit | commitdiff | tree |
| 2017-10-05 |
Clifford Wolf | Improve handling of Verific errors |
commit | commitdiff | tree |
| 2017-10-04 |
Clifford Wolf | Improve Verific error handling, check VHDL static asserts |
commit | commitdiff | tree |
| 2017-10-04 |
Clifford Wolf | Add blackbox command |
commit | commitdiff | tree |
| 2017-10-04 |
Clifford Wolf | Fix nasty bug in Verific bindings |
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| 2017-10-03 |
Clifford Wolf | Merge branch 'pr_ast_const_funcs' of https://github... |
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| 2017-10-03 |
Clifford Wolf | Merge branch 'fix_shift_reduce_conflict' of https:... |
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| 2017-10-03 |
Clifford Wolf | Merge branch 'dh73-master' |
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| 2017-10-03 |
Clifford Wolf | Rename "write_verilog -nobasenradix" to "write_verilog... |
commit | commitdiff | tree |
| 2017-10-02 |
dh73 | Tested and working altsyncarm without init files |
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| 2017-10-01 |
dh73 | Fixed wrong declaration in Verilog backend |
commit | commitdiff | tree |
| 2017-10-01 |
dh73 | Adding Cyclone IV (E, GX), Arria 10, Cyclone V and... |
commit | commitdiff | tree |
| 2017-09-30 |
Udi Finkelstein | Turned a few member functions into const, esp. dumpAst... |
commit | commitdiff | tree |
| 2017-09-30 |
Udi Finkelstein | Resolved classical Bison IF/THEN/ELSE shift/reduce... |
commit | commitdiff | tree |
| 2017-09-29 |
Clifford Wolf | Add first draft of eASIC back-end |
commit | commitdiff | tree |
| 2017-09-29 |
Clifford Wolf | Fix synth_ice40 doc regarding -top default |
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| 2017-09-29 |
Clifford Wolf | Allow $size and $bits in verilog mode, actually check... |
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| 2017-09-29 |
Clifford Wolf | Merge pull request #425 from udif/udif_dollar_bits |
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| 2017-09-28 |
Clifford Wolf | Merge pull request #421 from stephengroat/osx-travis |
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| 2017-09-27 |
Stephen | delete bad backslash |
commit | commitdiff | tree |
| 2017-09-27 |
Stephen | forgot to install bundles |
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| 2017-09-27 |
Stephen Groat | Add osx tests using brew bundle |
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| 2017-09-27 |
Clifford Wolf | Increase maximum LUT size in blifparse to 12 bits |
commit | commitdiff | tree |
| 2017-09-26 |
Udi Finkelstein | $size() now works correctly for all cases! |
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| 2017-09-26 |
Udi Finkelstein | $size() seems to work now with or without the optional... |
commit | commitdiff | tree |
| 2017-09-26 |
Clifford Wolf | Parse reals as string in JSON front-end |
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| 2017-09-26 |
Clifford Wolf | Merge branch 'vlogpp-inc-fixes' |
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| 2017-09-26 |
Clifford Wolf | Minor coding style fix |
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| 2017-09-26 |
Clifford Wolf | Merge branch 'master' of https://github.com/combinatory... |
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| 2017-09-26 |
Udi Finkelstein | enable $bits() and $size() functions only when the... |
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