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yosys.git
2019-07-31
Eddie Hung
Restore old CO behaviour
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2019-07-31
Eddie Hung
Helper: SigSpec::operator[] to accept negative indices
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2019-07-26
Eddie Hung
Fix spacing
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2019-07-26
Eddie Hung
Update test_autotb doc to reflect default value of...
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2019-07-26
Eddie Hung
Add doc for "test_autotb -seed" option
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2019-07-26
Eddie Hung
Pop the CO bit from O
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2019-07-26
Eddie Hung
Allow adders/accumulators with 33 bits using CO output
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2019-07-24
Eddie Hung
Add copyright header, comment on cascade
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2019-07-23
Eddie Hung
Eliminate warnings by sizing O correctly
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2019-07-23
Eddie Hung
Typo for Y_WIDTH
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2019-07-23
Eddie Hung
Fix muxAB logic
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2019-07-23
Eddie Hung
Remove debug print
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2019-07-23
Eddie Hung
Simplify and fix for MACs
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2019-07-23
Eddie Hung
Fix typo
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2019-07-22
Eddie Hung
Fix spacing
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2019-07-22
Eddie Hung
Remove debug
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2019-07-22
Eddie Hung
Pack hi and lo registers separately
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2019-07-22
Eddie Hung
SigSpec::extract() to return as many bits as poss if...
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2019-07-22
Eddie Hung
Rename according to vendor doc TN1295
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2019-07-22
Eddie Hung
Pack Y register
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2019-07-22
Eddie Hung
opt and wreduce necessary for -dsp
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2019-07-22
Eddie Hung
Pack adders not just accumulators
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2019-07-22
Eddie Hung
Use minimum sized width wires
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2019-07-20
Eddie Hung
Restore old ffY behaviour
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2019-07-20
Eddie Hung
Cleanup
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2019-07-20
Eddie Hung
Indirection via $__soft_mul
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2019-07-19
Eddie Hung
Do not do sign extension in techmap; let packer do it
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2019-07-19
Eddie Hung
Merge remote-tracking branch 'origin/eddie/wreduce_add...
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2019-07-19
Eddie Hung
Add another test
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2019-07-19
Eddie Hung
Do not access beyond bounds
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2019-07-19
Eddie Hung
Add an SigSpec::at(offset, defval) convenience method
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2019-07-19
Eddie Hung
Wrap A and B in sigmap
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2019-07-19
Eddie Hung
Remove "top" from message
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2019-07-19
Eddie Hung
Merge remote-tracking branch 'origin/eddie/wreduce_add...
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2019-07-19
Eddie Hung
Also optimise MSB of $sub
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2019-07-19
Eddie Hung
Add one more test with trimming Y_WIDTH of $sub
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2019-07-19
Eddie Hung
Be more explicit
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2019-07-19
Eddie Hung
wreduce for $sub
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2019-07-19
Eddie Hung
Add tests for sub too
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2019-07-19
Eddie Hung
Add test
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2019-07-19
Eddie Hung
SigSpec::extract to take negative lengths
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2019-07-19
Eddie Hung
Do not $mul -> $__mul if A and B are less than maxwidth
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2019-07-19
Eddie Hung
Add DSP_MINWIDTH=11 for ice40 since ice40_dsp uses...
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2019-07-19
Eddie Hung
Add a DSP_MINWIDTH macro, and soft-logic for {A_WIDTH...
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2019-07-19
Eddie Hung
Fine tune ice40_dsp.pmg, add support for packing subset...
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2019-07-19
Eddie Hung
Add support for ice40 signed multipliers
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2019-07-19
Eddie Hung
Merge branch 'xc7dsp' into ice40dsp
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2019-07-19
Eddie Hung
Fix typo in B
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2019-07-19
Eddie Hung
Merge remote-tracking branch 'origin/eddie/signed_ice40...
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2019-07-19
David Shah
ice40: Fix test_dsp_model.sh
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2019-07-19
David Shah
ice40/cells_sim.v: Fix sign of J and K partial products
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2019-07-19
Eddie Hung
Use sign_headroom instead
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2019-07-19
David Shah
ice40/cells_sim.v: LSB of A/B only signed in 8x8 mode
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2019-07-19
Eddie Hung
Add tests for all combinations of A and B signedness...
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2019-07-19
Eddie Hung
Don't copy ref if exists already
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2019-07-19
Eddie Hung
Fix SB_MAC sim model -- do not sign extend internal...
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2019-07-19
Eddie Hung
Add params
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2019-07-19
Eddie Hung
Merge remote-tracking branch 'origin/master' into ice40dsp
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2019-07-19
Eddie Hung
Merge remote-tracking branch 'origin/master' into xc7dsp
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2019-07-18
Eddie Hung
Do not define `DSP_SIGNEDONLY macro if no exists
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2019-07-18
Eddie Hung
Merge remote-tracking branch 'origin/master' into ice40dsp
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2019-07-18
Eddie Hung
ice40_dsp to accept $__MUL16X16 too
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2019-07-18
Eddie Hung
synth_ice40 to decompose into 16x16
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2019-07-18
Eddie Hung
mul2dsp to create cells that can be interchanged with...
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2019-07-18
Eddie Hung
Check if RHS is empty first
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2019-07-18
Eddie Hung
Make consistent
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2019-07-18
Eddie Hung
Do not autoremove ffP aor muxP
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2019-07-18
Eddie Hung
Improve pattern matcher to match subsets of $dffe?...
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2019-07-18
Eddie Hung
Improve A/B reg packing
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2019-07-18
Eddie Hung
Do not autoremove A/B registers since they might have...
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2019-07-18
Eddie Hung
Fix xilinx_dsp index cast
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2019-07-18
Eddie Hung
Fix signed multiplier decomposition
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2019-07-18
Eddie Hung
Use single DSP_SIGNEDONLY macro
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2019-07-18
David Shah
Merge pull request #1208 from ZirconiumX/intel_cleanups
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2019-07-18
Dan Ravensloft
synth_intel: Use stringf
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2019-07-18
Eddie Hung
Working for unsigned
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2019-07-18
David Shah
Merge pull request #1207 from ZirconiumX/intel_new_pass...
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2019-07-18
Dan Ravensloft
synth_intel: s/not family/no family/
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2019-07-18
Eddie Hung
Cleanup
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2019-07-18
Dan Ravensloft
synth_intel: revert change to run_max10
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2019-07-18
Ben Widawsky
intel_synth: Fix help message
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2019-07-18
Ben Widawsky
intel_synth: Small code cleanup to remove if ladder
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2019-07-18
Ben Widawsky
intel_synth: Make family explicit and match
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2019-07-18
Ben Widawsky
intel_synth: Minor code cleanups
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2019-07-18
Dan Ravensloft
synth_intel: rename for consistency with #1184
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2019-07-18
Eddie Hung
Wrong wildcard symbol
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2019-07-18
Eddie Hung
Merge branch 'xc7dsp' of github.com:YosysHQ/yosys into...
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2019-07-18
Clifford Wolf
Merge pull request #1184 from whitequark/synth-better...
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2019-07-18
Clifford Wolf
Merge pull request #1203 from whitequark/write_verilog...
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2019-07-18
David Shah
mul2dsp: Lower partial products always have unsigned...
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2019-07-17
Eddie Hung
Make all operands signed
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2019-07-17
Eddie Hung
Update comment
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2019-07-17
Eddie Hung
Pattern matcher to check pool of bits, not exactly
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2019-07-17
Eddie Hung
Fix mul2dsp signedness
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2019-07-17
Eddie Hung
A_SIGNED == B_SIGNED so flip both
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2019-07-17
Eddie Hung
SigSpec::remove_const() to return SigSpec&
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2019-07-17
Clifford Wolf
Remove old $pmux_safe code from write_verilog
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2019-07-17
David Shah
Merge pull request #1204 from smunaut/fix_1187
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2019-07-16
Eddie Hung
Add DSP_{A,B}_SIGNEDONLY macro
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2019-07-16
Eddie Hung
Signedness
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