riscv-isa-sim.git
2014-02-07 Andrew WatermanClear EVEC LSBs, which kindly prevents a segfault
2014-02-06 Andrew WatermanFix disassembly of JAL
2014-02-06 Yunsup Leecommit missing definitions for uarch counters
2014-02-04 Quan NguyenMove half precision instructions, add vfmsv, vfmvv
2014-02-01 Andrew WatermanFix linking on Darwin
2014-01-29 Christopher... Disasm now translates xor x0,x0,x0 as a machine-generat...
2014-01-28 Andrew WatermanForce extension loaders to be linked in
2014-01-27 Andrew WatermanEnable runtime loading of dynamic library with --extlib
2014-01-27 Andrew WatermanPrefer libraries located in current directory
2014-01-27 Andrew WatermanEliminate hwacha <-> riscv circular dependence
2014-01-27 Andrew WatermanLink subproject dynamic libraries correctly
2014-01-26 Andrew WatermanMerge softfloat_riscv into softfloat
2014-01-24 Andrew WatermanRequire libdl for dynamic linking at runtime
2014-01-24 Andrew WatermanDisassemble amoxor
2014-01-24 Andrew WatermanBuild and use shared libraries only
2014-01-24 Andrew WatermanBuild and use shared libraries
2014-01-24 Andrew WatermanHandle CSR permissions correctly
2014-01-22 Andrew WatermanUse auto-generated trap cause numbers
2014-01-21 Quan NguyenMerge branch 'confprec'
2014-01-16 Andrew WatermanInitialize tohost and fromhost to zero
2014-01-14 Andrew WatermanImprove performance for branchy code
2013-12-17 Andrew WatermanSpeed things up quite a bit
2013-12-09 Andrew WatermanNew RDCYCLE encoding
2013-11-30 Quan NguyenRemove debug printf in vsetprec
2013-11-30 Quan NguyenAdd vsetprec instruction prototype
2013-11-25 Andrew WatermanUpdate to new privileged ISA
2013-11-25 Quan NguyenMerge branch 'master' of github.com:ucb-bar/riscv-isa...
2013-11-21 Yunsup Leefix slli/slliw encoding bug
2013-11-06 Yunsup Leeadd accelerator disabled cause
2013-11-06 Yunsup Leecorrectly trap when SR_EA is disabled
2013-11-05 Albert OuFix declaration of half-precision instructions
2013-11-05 Albert OuRe-add Hwacha header file
2013-11-05 Albert OuImplement "half-baked" half-precision instruction subse...
2013-11-05 Albert OuMerge branch 'master' of github.com:ucb-bar/riscv-isa...
2013-10-29 Yunsup Leeinclude stdexcept
2013-10-29 Andrew WatermanPass target machine's return code back to OS
2013-10-28 Quan NguyenAdd missing fcvt opcodes through riscv-opcodes
2013-10-22 Yunsup Leeclarify vxcptsave/vxctkill semantics
2013-10-19 Yunsup Leeimplement vxcptsave/vxcptrestore
2013-10-19 Yunsup Leeclean up SR_EA, the enable accelerator bit in status reg
2013-10-19 Yunsup Leemore hwacha supervisor stuff
2013-10-19 Yunsup Leerefactor disassembler, and add hwacha disassembler
2013-10-18 Yunsup Leecan't execute frsr/fssr on ut
2013-10-18 Yunsup Leeor into control thread's fp exceptions
2013-10-18 Quan NguyenAdd empty opcode header files for half-precision
2013-10-18 Yunsup Leecatch trap_illegal_instruction in hwacha
2013-10-18 Yunsup Leeadd hwacha exception support
2013-10-18 Yunsup Leefix custom-1 rocc encoding
2013-10-16 Yunsup Leefix maxvl calc logic
2013-10-16 Yunsup Leeuse reset virtual method
2013-10-16 Yunsup Leeuse uint32_t for vl
2013-10-16 Yunsup Leefix missing null check when there's no extension
2013-10-16 Yunsup Leerevamp hwacha; now runs in physical mode
2013-10-15 Stephen TwiggPropogate the reset call to the extensions as well...
2013-10-15 Stephen TwiggFix bug where xs2 was not being properly respected.
2013-10-10 Yunsup Leecommit configure script; new configure option --enable...
2013-09-27 Christopher... Added commit logging (--enable-commitlog). Also fixed...
2013-09-27 Andrew WatermanUse WRITE_RD/WRITE_FRD macros to write registers
2013-09-27 Andrew WatermanBye, CB
2013-09-23 Scott Beamerfixes compile bug for not being able to find std::logic...
2013-09-23 Andrew WatermanFix Scott's deadlock
2013-09-22 Stephen TwiggAdjust rocc_inst_t to properly extract fields due to...
2013-09-21 Andrew WatermanUpdate ISA encoding and AUIPC semantics
2013-09-15 Andrew WatermanAdd helper disassembly program
2013-09-15 Andrew WatermanISA changes
2013-09-11 Andrew WatermanAdd AMOXOR
2013-09-11 Andrew WatermanImplement zany immediates
2013-09-10 Andrew WatermanDon't tick HTIF as often
2013-09-10 Andrew WatermanAdd rd field to JAL; drop J
2013-08-18 Andrew WatermanRenumber PCRs
2013-08-13 Andrew WatermanAdd test program for dummy rocc
2013-08-13 Andrew WatermanImplement RoCC and add a dummy RoCC
2013-08-12 Andrew WatermanInstructions are no longer member functions
2013-08-08 Andrew WatermanIgnore JALR's effective address LSB
2013-08-08 Andrew WatermanDisentangle some header files
2013-08-08 Andrew WatermanRename MTFSR/MFFSR to FSSR/FRSR
2013-08-08 Andrew WatermanSwap J and JALR encoding
2013-08-01 Quan NguyenFix eret (again)
2013-07-31 Andrew WatermanFix dumb ERET bug
2013-07-29 Andrew WatermanDon't flush TLB on PTBR writes (only FATC)
2013-07-27 Andrew WatermanNew supervisor mode
2013-07-27 Andrew WatermanRemove more vector stuff
2013-07-27 Andrew WatermanRename MFTX/MXTF to FMV
2013-07-26 Andrew WatermanRip out Hwacha for now
2013-07-26 Andrew WatermanRip out RVC for now
2013-07-26 Andrew WatermanGenerate instruction decoder dynamically
2013-07-25 Andrew WatermanRemove JALR static hints
2013-07-23 Andrew WatermanKill spike when xspike is SIGINTed
2013-07-22 Andrew WatermanDon't use stdout for debugging
2013-07-22 Andrew WatermanAdd xspike program
2013-07-20 Andrew WatermanUse calloc to allocate target memory
2013-07-13 Andrew WatermanEliminate infinite loop in debug mode
2013-07-13 Andrew WatermanExit cleanly from debug console
2013-07-13 Andrew WatermanFavor procs.size() over num_cores()
2013-07-13 Andrew WatermanFix SR_U64 bit being ignored
2013-06-03 Andrew Watermanmake spike.o correctly depend on dispatch.h
2013-06-03 Andrew Watermanuse coreutils `seq' instead of hacky `range'
2013-05-15 Yunsup Leechange riscv-isa-run to spike in documentation
2013-05-15 Yunsup Leefix make issue
2013-05-14 Yunsup Leechange riscv-isa-run to spike
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