yosys.git
2016-03-19 Clifford WolfAdded $display %m support, fixed mem leak in $display...
2016-03-19 Clifford WolfAdded black box modules for all the 7-series design...
2016-03-18 Clifford WolfFixed localparam signdness, fixes #127
2016-03-18 Clifford WolfSet "nosync" attribute on internal task/function wires
2016-03-15 Clifford WolfFixed Verilog parser fix and more similar improvements
2016-03-15 Andrew BeckerUse left-recursive rule for cell_port_list in Verilog...
2016-03-14 Clifford WolfBugfix in write_verilog for RTLIL processes
2016-03-11 Clifford WolfCleanups and improvements in examples/cmos/
2016-03-11 Clifford WolfMerge commit 'b34385ec924b6067c1f82bdbae923f8062518956'
2016-03-10 Clifford WolfFixed typos in verilog_defaults help message
2016-03-08 Clifford WolfAdded "write_edif -nogndvcc"
2016-03-08 Clifford WolfAdded examples/cxx-api/evaldemo.cc
2016-03-07 Clifford WolfMerge branch 'master' of github.com:cliffordwolf/yosys
2016-03-07 Clifford WolfUsing "mfs" and "lutpack" in ABC lut mapping
2016-03-05 Uros PlatiseCompleted ngspice digital example with verilog tb
2016-03-02 Clifford WolfAdded digital (xspice) example code to examples/cmos/
2016-03-02 Clifford WolfBe more conservative with net names in spice output
2016-02-29 Clifford WolfMerge pull request #119 from SebKuzminsky/spelling...
2016-02-28 Sebastian Kuzminskyuser-facing spelling fixes
2016-02-26 Clifford WolfWe are now in 0.6+ development
2016-02-26 Clifford WolfYosys 0.6 yosys-0.6
2016-02-24 Clifford WolfFixed BLIF parser for empty port assignments
2016-02-15 Clifford WolfUse easyer-to-read unoptimized ceil_log2()
2016-02-15 Clifford WolfUpdated ABC to ae7d65e71adc
2016-02-14 Clifford WolfUpdated command reference in manual
2016-02-14 Clifford WolfChangelog for upcoming 0.6 release
2016-02-14 Clifford WolfFixed more visual studio warnings
2016-02-13 Clifford WolfFixed some visual studio warnings
2016-02-13 Clifford WolfMerge branch 'master' of github.com:cliffordwolf/yosys
2016-02-13 Clifford WolfAdded "int ceil_log2(int)" function
2016-02-13 Clifford WolfFixed MXE ABC build
2016-02-13 Clifford WolfRun dffsr2dff in synth_xilinx
2016-02-13 Clifford WolfSupport for more Verific primitives (patch I got per...
2016-02-08 Clifford WolfUpdated ABC
2016-02-07 Clifford WolfWork around DDR dout sim glitches in ice40 SB_IO sim...
2016-02-07 Clifford WolfUpdated ABC
2016-02-04 Clifford WolfAdded "stat -liberty" for calculating chip area
2016-02-03 Clifford WolfBugfix in Verific front-end
2016-02-02 Clifford WolfUpdated verific build instructions
2016-02-02 Clifford WolfImproved dffsr2dff pass
2016-02-02 Clifford WolfAdded dffsr2dff
2016-02-02 Clifford WolfAdded addBufGate module method
2016-02-02 Clifford WolfUse alphanumerical order instead of idstring idx in...
2016-02-01 Clifford WolfAdded CodeOfConduct
2016-02-01 Clifford WolfUpdated ABC to hg rev ee212a9e94df
2016-02-01 Clifford WolfProgress in cell library documentation
2016-02-01 Clifford WolfAdded "abc -luts" option, Improved Xilinx logic mapping
2016-02-01 Clifford WolfImprovements in dfflibmap (FFs with Q/QN outputs, DFFs...
2016-02-01 Clifford WolfSigMap performance improvement
2016-02-01 Clifford Wolfhashlib mfp<> performance improvements
2016-01-31 Clifford WolfAdded reserve() method to haslib classes and
2016-01-31 Clifford WolfMerge branch 'rtlil_remove2_speedup' of https://github...
2016-01-31 Clifford WolfMore clang sanitizer stuff
2016-01-31 Rick Altherrrtlil: Improve performance of SigSpec::extract(SigSpec...
2016-01-31 Rick Altherrrtlil: speed up SigSpec::sort_and_unify()
2016-01-31 Rick Altherrrtlil: improve performance of SigSpec::replace(SigSpec...
2016-01-31 Rick Altherrgenrtlil: avoid converting SigSpec to set<SigBit> when...
2016-01-31 Rick Altherrrtlil: improve performance of SigSpec::remove2(SigSpec...
2016-01-31 Clifford WolfMeaningless coding style change
2016-01-31 Clifford WolfMerge branch 'rtlil_remove2_speedup' of https://github...
2016-01-31 Clifford WolfAddedd clang sanitizers
2016-01-30 Rick Altherrrtlil: rewrite remove2() to avoid copying
2016-01-30 Rick Altherrrtlil: duplicate remove2() for std::set<>
2016-01-30 Rick Altherrrtlil: change IdString comparison operators to take...
2016-01-08 Clifford WolfAdded "equiv_struct -fwonly"
2016-01-08 Clifford WolfBugfixes in equiv_struct
2016-01-08 Clifford WolfAdded "submod -copy"
2016-01-06 Clifford WolfAdded "write_blif -cname" mode
2016-01-06 Clifford WolfAdded "equiv_struct -maxiter <N>"
2016-01-06 Clifford WolfAdded "equiv_add -try" mode
2015-12-22 Clifford WolfFixed "splitnets -ports" for hierarchical designs
2015-12-22 Clifford WolfRe-run ice40_opt in "synth_ice40 -abc2"
2015-12-22 Clifford WolfImprovements in ice40_opt
2015-12-22 Clifford WolfBugfix in ice40_ffinit
2015-12-22 Clifford WolfImproved ice40_ffinit
2015-12-22 Clifford WolfRun opt_const before check in default scripts
2015-12-20 Clifford WolfAdded %R select expression
2015-12-20 Clifford WolfVarious improvements in BLIF front-end
2015-12-20 Clifford WolfAdded yosys-smtbmc -S
2015-12-15 Clifford WolfMerge pull request #110 from scanlime/master
2015-12-15 Micah Elizabeth... Mac build fix, gsed -> sed
2015-12-15 Micah Elizabeth... Remove nonportable "-r" option from xargs
2015-12-08 Clifford WolfAdded "synth_ice40 -abc2"
2015-12-07 Clifford WolfMerge pull request #108 from cseed/master
2015-12-06 Cotton SeedAdded LO to ICESTORM_LC for LUT cascade route.
2015-12-02 Clifford WolfImproved proc_mux performance for huge always blocks
2015-12-02 Clifford WolfAdded default values for hashlib at() methods
2015-11-30 Clifford WolfRe-added SigMap::allbits()
2015-11-30 Clifford WolfAdded tests/simple/graphtest.v
2015-11-29 Clifford WolfFixed oom bug in ilang parser
2015-11-27 Clifford WolfFixed performance bug in ilang parser
2015-11-26 Clifford WolfMerge branch 'master' of github.com:cliffordwolf/yosys
2015-11-26 Clifford WolfRemoved dangling ';' in rtlil.h
2015-11-26 Clifford WolfAdded ice40_ffinit pass
2015-11-24 Clifford WolfAdded PRIM_DLATCHRS support to verific front-end
2015-11-24 Clifford WolfFixed WE/RE usage in iCE40 BRAM mapping
2015-11-23 Clifford WolfFixed handling of re-declarations of wires in tasks...
2015-11-19 Clifford WolfAdded torder command
2015-11-16 Clifford WolfFixed performance bug in Verific importer
2015-11-12 Clifford WolfChanges for Verific 3.16_484_32_151112
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