yosys.git
2019-06-21 Eddie HungMerge remote-tracking branch 'origin/master' into xaig
2019-06-21 Eddie HungFix issue with part of PI being 1'bx
2019-06-21 Eddie HungCall opt_expr -mux_undef to get rid of 1'bx in muxes...
2019-06-21 Eddie HungHandle COs driven by 1'bx
2019-06-21 Eddie HungDo not call "setundef -zero" in abc9
2019-06-21 Eddie Hungwrite_xaiger to skip POs driven by 1'bx
2019-06-20 Clifford WolfFix typo, fixes #1095
2019-06-20 Clifford WolfImprove shregmap help message, fixes #1113
2019-06-20 Clifford WolfUpdate some .gitignore files
2019-06-20 Clifford WolfFix typo
2019-06-20 Clifford WolfMerge branch 'towoe-unpacked_arrays'
2019-06-20 Clifford WolfAdd proper test for SV-style arrays
2019-06-20 Clifford WolfMerge branch 'unpacked_arrays' of https://github.com...
2019-06-19 Eddie HungMerge pull request #1111 from acw1251/help_summary_fixes
2019-06-19 acw1251Fixed small typo in ice40_unlut help summary
2019-06-19 acw1251Fixed the help summary line for a few commands
2019-06-19 Eddie HungFix bug in #1078, add entry to CHANGELOG
2019-06-19 Clifford WolfMerge pull request #1109 from YosysHQ/clifford/fix1106
2019-06-19 Clifford WolfAdd "read_verilog -pwires" feature, closes #1106
2019-06-19 Clifford WolfMerge pull request #1105 from YosysHQ/clifford/fixlogicinit
2019-06-19 Tobias WölfelUnpacked array declaration using size
2019-06-19 Clifford WolfMake tests/aiger less chatty
2019-06-19 Clifford WolfAdd defvalue test, minor autotest fixes for .sv files
2019-06-19 Clifford WolfUse input default values in hierarchy pass
2019-06-19 Clifford WolfAdd defaultvalue attribute
2019-06-19 Clifford WolfFix handling of "logic" variables with initial value
2019-06-19 Clifford WolfMerge pull request #1100 from bwidawsk/home
2019-06-19 Clifford WolfMerge pull request #1104 from whitequark/case-semantics
2019-06-19 whitequarkExplain exact semantics of switch and case rules in...
2019-06-19 whitequarkIn RTLIL::Module::check(), check process invariants.
2019-06-18 Ben WidawskySupport filename rewrite in backends
2019-06-18 Ben WidawskySupport ~ for home directory
2019-06-18 Eddie HungReally permute Xilinx LUT mappings as default LUT6...
2019-06-18 Eddie HungRevert "Fix (do not) permute LUT inputs, but permute...
2019-06-18 Eddie HungClean up
2019-06-18 Eddie HungFix (do not) permute LUT inputs, but permute mux selects
2019-06-18 Clifford WolfMerge pull request #1086 from udif/pr_elab_sys_tasks2
2019-06-18 Eddie HungFix copy-pasta issue
2019-06-18 Eddie HungPermute INIT for +/xilinx/lut_map.v
2019-06-18 Eddie HungSimplify comment
2019-06-18 Eddie HungUpdate LUT7/8 delays to take account for [ABC]OUTMUX...
2019-06-17 Eddie Hung&scorr before &sweep, remove &retime as recommended
2019-06-17 Eddie HungCopy not move parameters/attributes
2019-06-17 Eddie HungFix leak removing cells during ABC integration; also...
2019-06-17 Eddie HungTry -W 300
2019-06-17 Eddie HungRe-enable &dc2
2019-06-16 Clifford WolfAdd timescale and generated-by header to yosys-smtbmc...
2019-06-16 Eddie HungCleanup
2019-06-15 Eddie HungFix upper XC7 LUT[78] delays to use I[01] -> O delay...
2019-06-14 Eddie HungLeave breadcrumb behind
2019-06-14 Eddie HungRemove redundant condition
2019-06-14 Eddie HungRevert "Cleanup/optimise toposort in write_xaiger"
2019-06-14 Eddie HungUpdate comment
2019-06-14 Eddie HungCheck that whiteboxes are synthesisable
2019-06-14 Eddie HungGet rid of compiler warnings
2019-06-14 Eddie HungAs per @daveshah1 remove async DFF timing from xilinx
2019-06-14 Eddie HungCover __APPLE__ too for little to big endian
2019-06-14 Eddie HungUpdate abc9 -D doc
2019-06-14 Eddie HungEnable "abc9 -D <num>" for timing-driven synthesis
2019-06-14 Eddie HungFurther cleanup based on @daveshah1
2019-06-14 Eddie HungResolve comments from @daveshah1
2019-06-14 Eddie HungAdd XC7_WIRE_DELAY macro to synth_xilinx.cc
2019-06-14 Eddie HungUpdate delays based on SymbiFlow/prjxray-db
2019-06-14 Eddie HungRename +/xilinx/abc.{box,lut} -> abc_xc7.{box,lut}
2019-06-14 Eddie HungComment out dist RAM boxing on ECP5 for now
2019-06-14 Eddie HungRemove WIP ABC9 flop support
2019-06-14 Eddie HungMerge remote-tracking branch 'origin/master' into xaig
2019-06-14 Eddie HungMake doc consistent
2019-06-14 Eddie HungCleanup
2019-06-14 Eddie HungMerge branch 'xaig' of github.com:YosysHQ/yosys into...
2019-06-14 Eddie HungMerge pull request #1097 from YosysHQ/dave/xaig_ecp5
2019-06-14 Eddie HungCleanup
2019-06-14 Eddie HungCleanup/optimise toposort in write_xaiger
2019-06-14 Eddie HungRemove extra semicolon
2019-06-14 Eddie HungAdd TODO to parse_xaiger
2019-06-14 David Shahecp5: Add abc9 option
2019-06-14 Eddie HungOptimise some more
2019-06-13 Eddie HungMove ConstEvalAig to aigerparse.cc
2019-06-13 Eddie HungFix name clash
2019-06-13 Eddie HungMore slimming
2019-06-13 Eddie HungAdd ConstEvalAig specialised for AIGs
2019-06-13 Eddie HungUpdate CHANGELOG with "synth -abc9"
2019-06-13 Eddie HungFix LP SB_LUT4 timing
2019-06-13 Eddie HungMore accurate CHANGELOG
2019-06-13 Serge BazanskiMerge pull request #829 from abdelrahmanhosny/master
2019-06-12 Eddie HungUpdate CHANGELOG
2019-06-12 Eddie HungRip out all non FPGA stuff from abc9
2019-06-12 Eddie HungFix spelling
2019-06-12 Eddie HungRevert "For 'stat' do not count modules with abc_box_id"
2019-06-12 Eddie HungRevert "Merge remote-tracking branch 'origin/eddie...
2019-06-12 Eddie HungMove neg-pol to pos-pol mapping from ff_map to cells_map.v
2019-06-12 Eddie HungBe more precise when connecting during ABC9 re-integration
2019-06-12 Eddie HungRemove unnecessary undriven_bits.insert
2019-06-12 Eddie HungRemove hacky wideports_split from abc9
2019-06-12 Eddie HungFix compile errors when #if 1 for debug
2019-06-12 Eddie Hungparse_xaiger to cope with inouts
2019-06-12 Eddie Hungwrite_xaiger to preserve POs even if driven by constant
2019-06-12 Eddie HungAdd a couple more tests
2019-06-12 Eddie HungDo not call abc9 if no outputs
2019-06-12 Eddie HungMore write_xaiger cleanup
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