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yosys.git
2019-07-18
Clifford Wolf
Merge pull request #1184 from whitequark/synth-better...
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2019-07-18
Clifford Wolf
Merge pull request #1203 from whitequark/write_verilog...
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2019-07-17
Clifford Wolf
Remove old $pmux_safe code from write_verilog
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2019-07-17
David Shah
Merge pull request #1204 from smunaut/fix_1187
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2019-07-16
Sylvain Munaut
ice40: Adapt the relut process passes to the new $lut...
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2019-07-16
whitequark
write_verilog: dump zero width constants correctly.
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2019-07-16
Eddie Hung
Merge pull request #1202 from YosysHQ/cmp2lut_lut6
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2019-07-16
whitequark
synth_ecp5: rename dram to lutram everywhere.
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2019-07-16
whitequark
synth_{ice40,ecp5}: more sensible pass label naming.
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2019-07-16
Eddie Hung
gen_lut to return correctly sized LUT mask
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2019-07-16
Eddie Hung
Forgot to commit
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2019-07-16
Eddie Hung
Add tests for cmp2lut on LUT6
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2019-07-16
Eddie Hung
Merge pull request #1188 from YosysHQ/eddie/abc9_push_i...
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2019-07-16
Eddie Hung
Merge pull request #1186 from YosysHQ/eddie/abc9_ice40_fix
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2019-07-16
Clifford Wolf
Merge pull request #1200 from mmicko/fix_typo_liberty_cc
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2019-07-16
Clifford Wolf
Merge pull request #1199 from mmicko/extract_fa_fix
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2019-07-16
Miodrag Milanovic
Fix typo, double "of"
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2019-07-16
Miodrag Milanovic
Fix check logic in extract_fa
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2019-07-15
Eddie Hung
Merge pull request #1196 from YosysHQ/eddie/fix1178
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2019-07-15
Eddie Hung
$__ICE40_CARRY_LUT4 -> $__ICE40_FULL_ADDER as per ...
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2019-07-15
Clifford Wolf
Merge pull request #1189 from YosysHQ/eddie/fix1151
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2019-07-15
Clifford Wolf
Merge pull request #1190 from YosysHQ/eddie/fix_1099
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2019-07-15
Clifford Wolf
Merge pull request #1191 from whitequark/opt_lut-log_debug
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2019-07-15
Clifford Wolf
Merge pull request #1195 from Roman-Parise/master
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2019-07-15
Clifford Wolf
Merge pull request #1197 from nakengelhardt/handle...
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2019-07-15
Eddie Hung
Revert "Add log_checkpoint function and use it in opt_m...
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2019-07-15
N. Engelhardt
smt: handle failure of setrlimit syscall
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2019-07-15
Eddie Hung
Revert "Fix first divergence in #1178"
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2019-07-15
Eddie Hung
Merge branch 'master' into eddie/fix1178
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2019-07-15
Clifford Wolf
Redesign log_id_cache so that it doesn't keep IdString...
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2019-07-15
Clifford Wolf
Add log_checkpoint function and use it in opt_muxtree
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2019-07-14
Eddie Hung
Merge pull request #1194 from cr1901/miss-semi
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2019-07-14
William D....
Fix missing semicolon in Windows-specific code in aiger...
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2019-07-14
Roman-Parise
Updated FreeBSD dependencies in README.md
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2019-07-13
whitequark
opt_lut: make less chatty.
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2019-07-13
Eddie Hung
If ConstEval fails do not log_abort() but return gracefully
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2019-07-13
Eddie Hung
Error out if enable > dbits
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2019-07-13
Eddie Hung
ice40_opt to $__ICE40_CARRY_LUT4 into $lut not SB_LUT
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2019-07-13
Eddie Hung
Add comment
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2019-07-13
Eddie Hung
Update test with more accurate LUT mask
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2019-07-13
Eddie Hung
duplicate -> clone
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2019-07-13
Eddie Hung
More cleanup
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2019-07-13
Eddie Hung
Cleanup
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2019-07-13
Eddie Hung
Cleanup
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2019-07-13
Eddie Hung
Cleanup
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2019-07-13
Eddie Hung
More cleanup
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2019-07-13
Eddie Hung
Cleanup
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2019-07-13
Eddie Hung
Cleanup
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2019-07-13
Eddie Hung
Cleanup
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2019-07-12
Eddie Hung
Do not double count cells in abc
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2019-07-12
Clifford Wolf
Merge pull request #1183 from whitequark/ice40-always...
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2019-07-12
Eddie Hung
Use Const::from_string() not its constructor...
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2019-07-12
Eddie Hung
Off by one
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2019-07-12
Eddie Hung
Fix spacing
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2019-07-12
Eddie Hung
Remove double push
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2019-07-12
Eddie Hung
Map to and from this box if -abc9
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2019-07-12
Eddie Hung
ice40_opt to handle this box and opt back to SB_LUT4
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2019-07-12
Eddie Hung
Add new box to cells_sim.v
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2019-07-12
Eddie Hung
_ABC macro will map and unmap to this new box
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2019-07-12
Eddie Hung
Combine SB_CARRY+SB_LUT into one $__ICE40_CARRY_LUT4 box
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2019-07-11
whitequark
synth_ice40: switch -relut to be always on.
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2019-07-11
whitequark
synth_ice40: fix help text typo. NFC.
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2019-07-11
Eddie Hung
Merge pull request #1182 from koriakin/xc6s-bram
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2019-07-11
Eddie Hung
Merge pull request #1185 from koriakin/xc-ff-init-vals
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2019-07-11
Marcin Kościelnicki
xilinx: Fix the default values for FDPE/FDSE INIT attri...
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2019-07-11
Eddie Hung
Enable &mfs for abc9, even if it only currently works...
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2019-07-11
Marcin Kościelnicki
synth_xilinx: Initial Spartan 6 block RAM inference...
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2019-07-11
Clifford Wolf
Merge pull request #1172 from whitequark/write_verilog...
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2019-07-11
Clifford Wolf
Merge pull request #1179 from whitequark/attrmap-proc
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2019-07-10
Eddie Hung
Merge pull request #1180 from YosysHQ/eddie/no_abc9_retime
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2019-07-10
Eddie Hung
Merge pull request #1148 from YosysHQ/xc7mux
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2019-07-10
Eddie Hung
Error out if -abc9 and -retime specified
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2019-07-10
Eddie Hung
Add some spacing
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2019-07-10
Eddie Hung
Add some ASCII art explaining mux decomposition
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2019-07-10
whitequark
attrmap: also consider process, switch and case attributes.
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2019-07-10
Clifford Wolf
Merge pull request #1177 from YosysHQ/clifford/async
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2019-07-10
Eddie Hung
Call muxpack and pmux2shiftx before cmp2lut
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2019-07-09
Eddie Hung
Fix first divergence in #1178
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2019-07-09
Eddie Hung
Restore opt_clean back to original place
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2019-07-09
Eddie Hung
Restore missing techmap -map +/cmp2lut.v with LUT_WIDTH=6
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2019-07-09
David Shah
synth_ecp5: Fix typo in copyright header
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2019-07-09
Clifford Wolf
Merge pull request #1174 from YosysHQ/eddie/fix1173
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2019-07-09
Clifford Wolf
Merge pull request #1175 from whitequark/write_verilog...
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2019-07-09
Clifford Wolf
Fix tests/various/async FFL test
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2019-07-09
Clifford Wolf
Improve tests/various/async, disable failing ffl test
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2019-07-09
Eddie Hung
Extend using A[1] to preserve don't care
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2019-07-09
Eddie Hung
Merge pull request #1171 from YosysHQ/revert-1166-eddie...
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2019-07-09
Eddie Hung
Merge remote-tracking branch 'origin/eddie/fix1173...
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2019-07-09
whitequark
write_verilog: fix placement of case attributes. NFC.
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2019-07-09
Eddie Hung
Increment _TECHMAP_BITS_CONNMAP_ by one since counting...
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2019-07-09
Clifford Wolf
Add tests/various/async.{sh,v}
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2019-07-09
Clifford Wolf
Improve tests/various/run-test.sh
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2019-07-09
Clifford Wolf
Add tests/simple_abc9/.gitignore
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2019-07-09
whitequark
write_verilog: write RTLIL::Sa aka - as Verilog ?.
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2019-07-09
Eddie Hung
Extend during mux decomposition with 1'bx
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2019-07-09
Eddie Hung
Fix typo and comments
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2019-07-09
Eddie Hung
Merge pull request #1170 from YosysHQ/eddie/fix_double_...
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2019-07-09
Eddie Hung
Merge remote-tracking branch 'origin/master' into xc7mux
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2019-07-09
Eddie Hung
synth_xilinx to call commands of synth -coarse directly
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2019-07-09
Eddie Hung
Revert "synth_xilinx to call "synth -run coarse" with...
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