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yosys.git
2019-03-14
Eddie Hung
Reverse bits in INIT parameter for Xilinx, since MSB...
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2019-03-14
Eddie Hung
Misspell
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2019-03-14
Eddie Hung
Revert "Add shregmap -init_msb_first and use in synth_x...
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2019-03-14
Eddie Hung
Merge remote-tracking branch 'origin/master' into xc7srl
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2019-03-14
Eddie Hung
Add shregmap -init_msb_first and use in synth_xilinx
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2019-03-14
Eddie Hung
Fix cells_map for SRL
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2019-03-14
Eddie Hung
Move shregmap until after first techmap
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2019-03-13
Eddie Hung
Refactor $__SHREG__ in cells_map.v
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2019-03-13
Clifford Wolf
Merge pull request #868 from YosysHQ/clifford/fixmem
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2019-03-12
Clifford Wolf
Fix a bug in handling quotes in multi-cmd lines in...
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2019-03-12
Clifford Wolf
Merge pull request #866 from YosysHQ/clifford/idstuff
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2019-03-12
Clifford Wolf
Remove ice40/cells_sim.v hack to avoid warning for...
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2019-03-12
Clifford Wolf
Improve handling of memories used in mem index expressi...
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2019-03-12
Clifford Wolf
Remove outdated "blocking assignment to memory" warning
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2019-03-12
Clifford Wolf
Only set MEM2REG_FL_CONST_LHS/MEM2REG_FL_VAR_LHS for...
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2019-03-11
Clifford Wolf
Improve determinism of IdString DB for similar scripts
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2019-03-11
Eddie Hung
Merge pull request #864 from YosysHQ/svalabelfix
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2019-03-11
Clifford Wolf
Add ENABLE_GLOB Makefile switch
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2019-03-10
Clifford Wolf
Fix handling of cases that look like sva labels, fixes...
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2019-03-09
Clifford Wolf
Fix typo in ice40_braminit help msg
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2019-03-09
Clifford Wolf
Merge pull request #859 from smunaut/ice40_braminit
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2019-03-09
Clifford Wolf
Fix signed $shift/$shiftx handling in write_smt2
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2019-03-09
Clifford Wolf
Add $dffsr support to async2sync
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2019-03-09
Clifford Wolf
Merge pull request #858 from YosysHQ/clifford/svalabels
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2019-03-09
Clifford Wolf
Merge pull request #861 from YosysHQ/verific_chparam
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2019-03-09
Clifford Wolf
Also add support for labels on sva module items, fixes...
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2019-03-09
Eddie Hung
Update help message for -chparam
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2019-03-09
Eddie Hung
Add -chparam option to verific command
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2019-03-09
Eddie Hung
Fix spelling
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2019-03-08
Clifford Wolf
Merge branch 'master' of github.com:YosysHQ/yosys
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2019-03-08
Clifford Wolf
Fix handling of task output ports in clocked always...
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2019-03-07
Sylvain Munaut
ice40: Run ice40_braminit pass by default
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2019-03-07
Sylvain Munaut
ice40: Add ice40_braminit pass to allow initialization...
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2019-03-07
Clifford Wolf
Merge pull request #856 from kprasadvnsi/master
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2019-03-07
Clifford Wolf
Use SVA label in smt export if available
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2019-03-07
Clifford Wolf
Add support for SVA labels in read_verilog
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2019-03-07
Clifford Wolf
Add hack for handling SVA labels via Verific
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2019-03-07
Clifford Wolf
Add link to SF2 / igloo2 macro library guide
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2019-03-07
Clifford Wolf
Improvements in sf2 cells_sim.v
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2019-03-06
Clifford Wolf
Add sf2 techmap rules for more FF types
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2019-03-06
Clifford Wolf
Refactor SF2 iobuf insertion, Add clkint insertion
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2019-03-06
Clifford Wolf
Improve igloo2 example
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2019-03-06
Clifford Wolf
Improve igloo2 example
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2019-03-06
Clifford Wolf
Improvements in SF2 flow and demo
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2019-03-06
Kali Prasad
examples/anlogic/ now also output the SVF file.
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2019-03-06
Eddie Hung
Fix spelling in pmgen/README.md
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2019-03-06
Clifford Wolf
Improve igloo2 exmaple
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2019-03-05
Clifford Wolf
Merge pull request #842 from litghost/merge_upstream
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2019-03-05
Clifford Wolf
Merge pull request #850 from daveshah1/ecp5_warn_conflict
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2019-03-05
Clifford Wolf
Add missing newline
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2019-03-05
Clifford Wolf
Merge pull request #851 from kprasadvnsi/master
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2019-03-05
Clifford Wolf
Merge pull request #852 from ucb-bar/firrtlfixes
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2019-03-05
Clifford Wolf
Use "write_edif -pvector bra" for Xilinx EDIF files
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2019-03-04
Jim Lawson
Ensure fid() calls make_id() for consistency; tests...
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2019-03-04
Kali Prasad
Added examples/anlogic/
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2019-03-04
Keith Rothman
Revert BRAM WRITE_MODE changes.
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2019-03-04
David Shah
ecp5: Demote conflicting FF init values to a warning
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2019-03-04
Clifford Wolf
Improve igloo2 example
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2019-03-04
Clifford Wolf
Update igloo2 example to Libero v12.0
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2019-03-03
Clifford Wolf
Merge pull request #848 from YosysHQ/clifford/fix763
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2019-03-03
Clifford Wolf
Merge pull request #849 from YosysHQ/clifford/dynports
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2019-03-02
Clifford Wolf
Only run derive on blackbox modules when ports have...
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2019-03-02
Clifford Wolf
Fix error for wire decl in always block, fixes #763
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2019-03-02
Clifford Wolf
Fix $global_clock handling vs autowire
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2019-03-02
Clifford Wolf
Merge pull request #847 from YosysHQ/clifford/fix785
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2019-03-02
Clifford Wolf
Fix $readmem[hb] for mem2reg memories, fixes #785
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2019-03-02
Clifford Wolf
Merge pull request #843 from YosysHQ/clifford/mem2regco...
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2019-03-02
Clifford Wolf
Merge pull request #845 from YosysHQ/clifford/travisnomacos
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2019-03-02
Clifford Wolf
Disable macOS builds in Travis
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2019-03-02
Larry Doolittle
Try again for passes/pmgen/ice40_dsp_pm.h rule
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2019-03-01
Keith Rothman
Revert FF models to include IS_x_INVERTED parameters.
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2019-03-01
Keith Rothman
Use singular for disabling of DRAM or BRAM inference.
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2019-03-01
Clifford Wolf
Minor improvements in README
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2019-03-01
Clifford Wolf
Use mem2reg on memories that only have constant-index...
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2019-03-01
Clifford Wolf
Fix "write_edif -gndvccy"
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2019-03-01
Keith Rothman
Modify arguments to match existing style.
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2019-03-01
Keith Rothman
Changes required for VPR place and route synth_xilinx.
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2019-03-01
Clifford Wolf
Merge pull request #841 from mmicko/master
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2019-03-01
Miodrag Milanovic
Fix ECP5 cells_sim for iverilog
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2019-03-01
Clifford Wolf
Improve "read" error msg
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2019-03-01
Clifford Wolf
Merge pull request #836 from elmsfu/ice40_2bit_ram_rw_mode
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2019-03-01
Clifford Wolf
Hotfix for "make test"
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2019-03-01
Clifford Wolf
Merge pull request #837 from YosysHQ/clifford/fix835
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2019-03-01
Clifford Wolf
Fix multiple issues in wreduce FF handling, fixes #835
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2019-03-01
Elms
ice40: use 2 bits for READ/WRITE MODE for SB_RAM map
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2019-02-28
Clifford Wolf
Merge pull request #834 from YosysHQ/clifford/siminit
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2019-02-28
Clifford Wolf
Add "write_verilog -siminit"
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2019-02-28
Larry Doolittle
Reduce amount of trailing whitespace in code base
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2019-02-28
Clifford Wolf
Fix pmgen for in-tree builds
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2019-02-28
Clifford Wolf
Merge pull request #794 from daveshah1/ecp5improve
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2019-02-28
Clifford Wolf
Merge pull request #827 from ucb-bar/firrtlfixes
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2019-02-28
Clifford Wolf
Fix pmgen for out-of-tree build
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2019-02-28
Eddie Hung
Remove SRL16/32 from cells_xtra
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2019-02-28
Eddie Hung
Add SRL16 and SRL32 sim models
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2019-02-28
Eddie Hung
Fix SRL16/32 techmap off-by-one
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2019-02-28
Clifford Wolf
Merge pull request #833 from YosysHQ/clifford/fix831
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2019-02-28
Clifford Wolf
Fix smt2 code generation for partially initialized...
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2019-02-28
Clifford Wolf
Merge pull request #832 from YosysHQ/supercover
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2019-02-28
Eddie Hung
synth_xilinx to call shregmap with enable support
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2019-02-28
Eddie Hung
synth_xilinx to use shregmap with -params too
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