litex.git
2012-03-15 Sebastien Bourdeauducqcorelogic: convert timeline to function and move to...
2012-03-14 Sebastien Bourdeauducqbus/asmibus/hub: require finalization before get_slots
2012-03-14 Sebastien Bourdeauducqfhdl: export log2_int
2012-03-10 Alain Péteutsetup.py: simplify
2012-03-10 Sebastien Bourdeauducqdoc: more examples and comments
2012-03-10 Sebastien Bourdeauducqdoc: cosmetic changes (thanks sh4rm4 for reporting...
2012-03-09 Sebastien Bourdeauducqdoc: use script font
2012-03-09 Sebastien Bourdeauducqdoc: simulation
2012-03-09 Sebastien Bourdeauducqdoc: cosmetic changes (thanks rofl0r for reporting...
2012-03-09 Sebastien Bourdeauducqdoc: add logo
2012-03-09 Sebastien Bourdeauducqdoc: switch to sphinx
2012-03-08 Sebastien Bourdeauducqexamples: FIR filter simulation
2012-03-08 Sebastien Bourdeauducqfhdl: handle negative constants correctly
2012-03-08 Sebastien Bourdeauducqexamples: remove outdated wb_intercon simulation
2012-03-08 Sebastien Bourdeauducqvpi: support extra include directories
2012-03-08 Sebastien Bourdeauducqgitignore: update
2012-03-08 Sebastien Bourdeauducqbus: generic transaction model
2012-03-08 Sebastien Bourdeauducqvpi: patch for Icarus Verilog
2012-03-08 Sebastien Bourdeauducqexamples: small cleanup
2012-03-08 Sebastien Bourdeauducqsim: fix zero encoding
2012-03-08 Sebastien Bourdeauducqsim: fix message debug formatting
2012-03-06 Sebastien Bourdeauducqsim: make initialization cycle optional (selectable...
2012-03-06 Sebastien Bourdeauducqsim: memory access
2012-03-06 Sebastien Bourdeauducqfhdl: register memory objects with namespace
2012-03-06 Sebastien Bourdeauducqsim: support for signed numbers
2012-03-06 Sebastien Bourdeauducqfhdl/verilog: fix signed constant conversion
2012-03-06 Sebastien Bourdeauducqvpi: install target
2012-03-06 Sebastien Bourdeauducqsim: VCD generation
2012-03-06 Sebastien Bourdeauducqsim: clean startup/shutdown
2012-03-06 Sebastien Bourdeauducqsim: remove temporary files and socket
2012-03-06 Sebastien Bourdeauducqfhdl/namer: do not reference objects with __del__ metho...
2012-03-06 Sebastien Bourdeauducqsim: remove default sockaddr
2012-03-06 Sebastien Bourdeauducqfhdl: add simulation functions in fragment
2012-03-05 Sebastien Bourdeauducqsim: basic functionality working
2012-03-05 Sebastien Bourdeauducqsim: signal writes working
2012-03-04 Sebastien Bourdeauducqsim: cleanups
2012-03-04 Sebastien Bourdeauducqsim: signal reads working
2012-03-04 Sebastien Bourdeauducqsim: compile VPI module
2012-03-04 Sebastien Bourdeauducqsim: two way IPC working
2012-03-03 Sebastien Bourdeauducqsim: IPC module (lacks str/int encoding)
2012-02-29 Sebastien BourdeauducqREADME: clarify license
2012-02-19 Sebastien Bourdeauducqbus/dfi: fix multiphase naming
2012-02-18 Sebastien Bourdeauducqbank/csrgen: fix RE generation
2012-02-17 Sebastien Bourdeauducqbank: add RE signal for registers made of fields
2012-02-17 Sebastien Bourdeauducqbus: add interconnect statements function
2012-02-17 Sebastien Bourdeauducqfhdl: check we pass BV to signals
2012-02-17 Sebastien Bourdeauducqfhdl/verilog: properly connect instance inouts
2012-02-16 Sebastien Bourdeauducqfhdl: support forwarding of bidirectional signals from...
2012-02-15 Sebastien Bourdeauducqbus/dfi: filter signals by direction
2012-02-15 Sebastien Bourdeauducqbank: omit device write register when access_bus==READ_...
2012-02-15 Sebastien Bourdeauducqbus: add DFI
2012-02-15 Sebastien Bourdeauducqbank/csrgen: use new bus API
2012-02-15 Sebastien Bourdeauducqbus: fix simple interconnect
2012-02-15 Sebastien Bourdeauducqbus: simplify and cleanup
2012-02-14 Sebastien Bourdeauducqbus/asmibus/hub: forward data and tag_call
2012-02-14 Sebastien BourdeauducqUse double quotes for all strings
2012-02-13 Sebastien Bourdeauducqbus/wishbone2asmi: cache hits working
2012-02-13 Sebastien Bourdeauducqcorelogic: support reverse in displacer/chooser
2012-02-13 Sebastien BourdeauducqFix syntax errors and other stupid problems
2012-02-13 Sebastien Bourdeauducqbus/csr: Rename a->adr d->dat to be consistent with...
2012-02-13 Sebastien Bourdeauducqdoc: update ASMI description
2012-02-13 Sebastien Bourdeauducqbus/wishbone2asmi: set WM, and send 0 when inactive
2012-02-13 Sebastien Bourdeauducqbus: Wishbone to ASMI caching bridge (untested)
2012-02-11 Sebastien Bourdeauducqcorelogic/misc: displacer + chooser
2012-02-11 Sebastien Bourdeauducqcorelogic/misc/multimux: less confusing variable name
2012-02-11 Sebastien Bourdeauducqbus/asmibus: fix typo
2012-02-11 Sebastien Bourdeauducqcorelogic/record: add to_signal convenience function
2012-02-11 Sebastien Bourdeauducqcorelogic/misc: contiguous split
2012-02-10 Sebastien Bourdeauducqbus/asmibus: add get_slots, fix get_fragment
2012-02-10 Sebastien Bourdeauducqbus: ASMI hub (untested)
2012-02-08 Sebastien Bourdeauducqdoc: update Bank description
2012-02-06 Sebastien Bourdeauducqbus/wishbone2csr: truncate WB data
2012-02-06 Sebastien Bourdeauducqfhdl: do not attempt slicing non-array signals to keep...
2012-02-06 Sebastien Bourdeauducqbank: event manager
2012-02-06 Sebastien Bourdeauducqbank: support registers larger than the bus word width
2012-02-06 Sebastien Bourdeauducqbank: refactoring
2012-02-06 Sebastien Bourdeauducqbank/csrgen: use enumerate
2012-02-05 Sebastien Bourdeauducqfhdl/structure: binary constant builder
2012-02-03 Sébastien BourdeauducqMerge pull request #2 from larsclausen/master
2012-02-02 Lars-Peter... Use enumerate(x) instead of zip(range(x), x)
2012-02-02 Lars-Peter... fhdl/namer: Add support for STORE_DEREF opcode
2012-02-02 Lars-Peter... Lower required python version to 3.1
2012-01-28 Sebastien Bourdeauducqexamples/wb_intercon: update to new APIs
2012-01-28 Sebastien Bourdeauducqfhdl/namer: extract variable names with bytecode inspection
2012-01-28 Sebastien Bourdeauducqfhdl: do not prefix instance signal names
2012-01-27 Sebastien BourdeauducqRemove explicit bus names and rely on the new automatic...
2012-01-27 Sebastien Bourdeauducqfhdl: support memory read enable
2012-01-27 Sebastien Bourdeauducqfhdl: make WRITE_FIRST default
2012-01-27 Sebastien Bourdeauducqdoc: memories
2012-01-27 Sebastien Bourdeauducqfhdl: memories working
2012-01-27 Sebastien Bourdeauducqfhdl/verilog: clean up signal classification and suppor...
2012-01-27 Sebastien Bourdeauducqfhdl/structure: memory description
2012-01-27 Sebastien Bourdeauducqdoc: cosmetic changes
2012-01-26 Sebastien Bourdeauducqdoc: ASMI description
2012-01-25 Sebastien BourdeauducqRemove duplicate logo
2012-01-25 Sebastien Bourdeauducqdoc: refactor
2012-01-21 Sebastien Bourdeauducqflow/ala: fix typo for And (thanks Lars)
2012-01-21 Sebastien BourdeauducqLogo
2012-01-20 Sebastien BourdeauducqUse meaningful class names
2012-01-20 Sebastien BourdeauducqInclude fragment pads in pre-naming dictionary
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