yosys.git
2014-08-04 Clifford WolfAdded RTLIL::IdString::in(...)
2014-08-03 Clifford WolfFixed "share" for memory read ports
2014-08-03 Clifford WolfAdded "wreduce" to some of the standard test benches
2014-08-03 Clifford WolfProgress in "wreduce" pass
2014-08-03 Clifford WolfAdded "wreduce" command (work in progress)
2014-08-03 Clifford WolfAdded query() API to ModIndex
2014-08-03 Clifford WolfAdded ID() macro for static IdStrings
2014-08-03 Clifford WolfImplemented recursive techmap
2014-08-03 Clifford WolfFixes in show command (related to new IdString)
2014-08-02 Clifford WolfImplemented simplemap support for "techmap -extern"
2014-08-02 Clifford WolfFixed a va_list corruption in logv_error()
2014-08-02 Clifford WolfBe more conservative with printing decimal numbers...
2014-08-02 Clifford WolfImproved verilog output for ordinary $mux cells
2014-08-02 Clifford WolfBugfix in "techmap -extern"
2014-08-02 Clifford WolfRemoved at() method from RTLIL::IdString
2014-08-02 Clifford WolfNo implicit conversion from IdString to anything else
2014-08-02 Clifford WolfMore bugfixes related to new RTLIL::IdString
2014-08-02 Clifford WolfLimit size of log_signal buffer to 100 elements
2014-08-02 Clifford WolfImprovements in new RTLIL::IdString implementation
2014-08-02 Clifford WolfFixed a performance bug in opt_reduce
2014-08-02 Clifford WolfImplemented new reference counting RTLIL::IdString
2014-08-02 Clifford WolfFixed memory corruption related to id2cstr()
2014-08-02 Clifford WolfMore cleanups related to RTLIL::IdString usage
2014-08-01 Clifford WolfPreparations for RTLIL::IdString redesign: cleanup...
2014-08-01 Clifford WolfAdded logfile hash to statistics footer
2014-08-01 Clifford WolfReplaced sha1 implementation
2014-08-01 Clifford WolfAdded per-pass cpu usage statistics
2014-08-01 Clifford WolfAdded ModIndex helper class, some changes to RTLIL...
2014-08-01 Clifford WolfPacked SigBit::data and SigBit::offset in a union
2014-08-01 Clifford WolfConsolidated hana test benches into fewer files
2014-08-01 Clifford WolfAdded "test_autotb -n <num_iter>" option
2014-07-31 Clifford WolfRenamed modwalker.h to modtools.h
2014-07-31 Clifford WolfVarious cleanups in Makefile, Renamed default configura...
2014-07-31 Clifford WolfAdded compiler + compiler version + compiler flags...
2014-07-31 Clifford WolfFixed build of verific bindings
2014-07-31 Clifford WolfRenamed port access function on RTLIL::Cell, added...
2014-07-31 Clifford WolfAdded "trace" command
2014-07-31 Clifford WolfAdded RTLIL::Monitor
2014-07-31 Clifford WolfAdded module->design and cell->module, wire->module...
2014-07-31 Clifford WolfMoved some stuff to kernel/yosys.{h,cc}, using Yosys...
2014-07-31 Clifford WolfRenamed "stdcells.v" to "techmap.v"
2014-07-31 Clifford WolfAdded "techmap -assert"
2014-07-31 Clifford WolfReorganized stdcells.v (no actual code change, just...
2014-07-30 Clifford WolfAdded "yosys -A"
2014-07-30 Clifford WolfAdded "yosys -Q"
2014-07-30 Clifford WolfAdded techmap CONSTMAP feature
2014-07-30 Clifford WolfFixed counting verilog line numbers for "// synopsys...
2014-07-30 Clifford WolfAdded write_file command
2014-07-30 Clifford WolfAdded "make -j{N}" support to "make test"
2014-07-30 Clifford WolfImprovements in test_cell
2014-07-30 Clifford WolfNew techmap default rules for $shr $sshr $shl $sshl
2014-07-30 Clifford WolfUsing native ezSAT shift ops in satgen, fixed $shift...
2014-07-30 Clifford WolfAdded native support for shift operations to ezSAT
2014-07-30 Clifford WolfAdded "log_dump_val_worker(char *v)"
2014-07-30 Clifford WolfAdded CodingStyle document
2014-07-30 Clifford WolfAdded "kernel/yosys.h" and "kernel/yosys.cc"
2014-07-29 Clifford WolfAdded "test_cell" command
2014-07-29 Clifford WolfRenamed "write_autotest" to "test_autotb" and moved...
2014-07-29 Clifford WolfFixed Verilog pre-processor for files with no trailing...
2014-07-29 Clifford WolfBugfix in simlib.v for iverilog
2014-07-29 Clifford WolfAllow "hierarchy -generate" for $__ cells
2014-07-29 Clifford WolfAdded "techmap -map %{design-name}"
2014-07-29 Clifford WolfAdded $shift and $shiftx cell types (needed for correct...
2014-07-28 Clifford WolfRemoved left over debug code
2014-07-28 Clifford WolfFixed part selects of parameters
2014-07-28 Clifford WolfSet results of out-of-bounds static bit/part select...
2014-07-28 Clifford WolfFixed RTLIL code generator for part select of parameter
2014-07-28 Clifford WolfFixed width detection for part selects
2014-07-28 Clifford WolfAdded support for "upto" wires to Verilog front- and...
2014-07-28 Clifford WolfAdded wire->upto flag for signals such as "wire [0...
2014-07-28 Clifford WolfUsing log_assert() instead of assert()
2014-07-28 Clifford WolfAdded std::initializer_list<> constructor to SigSpec
2014-07-28 Clifford WolfAdded cover() to all SigSpec constructors
2014-07-28 Clifford WolfFixed signdness detection of expressions with bit-...
2014-07-28 Clifford WolfImprovements in tests/vloghtb
2014-07-27 Clifford WolfAdded techmap -extern
2014-07-27 Clifford WolfAdded proper Design->addModule interface
2014-07-27 Clifford WolfAdded topological sorting to techmap
2014-07-27 Clifford WolfAdded SigPool::check(bit)
2014-07-27 Clifford WolfSmall improvements in PerformanceTimer API
2014-07-27 Clifford WolfFixed bug in opt_clean
2014-07-27 Clifford WolfImproved performance of opt_const on large modules
2014-07-27 Clifford WolfAdded RTLIL::SigSpec::remove_const() handling of packed...
2014-07-27 Clifford WolfAdded RTLIL::SigSpecConstIterator
2014-07-27 Clifford WolfFixed a bug in opt_clean and some RTLIL API usage cleanups
2014-07-27 Clifford WolfAdded log_cmd_error_expection
2014-07-27 Clifford WolfFixed verific bindings for new RTLIL api
2014-07-27 Clifford WolfFixed ilang parser for new RTLIL API
2014-07-27 Clifford WolfUsing new obj iterator API in a few places
2014-07-27 Clifford WolfAdded RTLIL::Module::wire(id) and cell(id) lookup functions
2014-07-27 Clifford WolfAdded RTLIL::Design::modules()
2014-07-27 Clifford WolfRefactoring: Renamed RTLIL::Design::modules to modules_
2014-07-27 Clifford WolfAdded conversion from ObjRange to std::vector and std...
2014-07-27 Clifford WolfAdded RTLIL::ObjIterator and RTLIL::ObjRange
2014-07-27 Clifford WolfUsing std::move() in SigSpec move constructor
2014-07-27 Clifford WolfAdded RTLIL::SigSpec move constructor and move assignme...
2014-07-27 Clifford WolfMostly cosmetic changes to rtlil.h
2014-07-26 Clifford WolfRefactoring: Renamed RTLIL::Module::cells to cells_
2014-07-26 Clifford WolfRefactoring: Renamed RTLIL::Module::wires to wires_
2014-07-26 Clifford WolfNew message for completion of build
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