yosys.git
2021-08-13 Rupert SwarbrickGenerate an RTLIL representation of bind constructs
2021-08-13 Marcelina KościelnickaAdd opt_mem_widen pass.
2021-08-13 Marcelina Kościelnickamemory_share: Add -nosat and -nowiden options.
2021-08-13 Marcelina Kościelnickamemory_dff: Recognize soft transparency logic.
2021-08-13 Marcelina KościelnickaAdd new opt_mem_priority pass.
2021-08-13 Miodrag MilanovićMerge pull request #2932 from YosysHQ/mwk/logger-check...
2021-08-13 Brett Witherspoonsv: improve support for wire and var with user-defined...
2021-08-13 github-actions... Bump version
2021-08-12 Marcelina Kościelnickamemory_share: Pass addresses through sigmap_xmux everyw...
2021-08-12 Marcelina Kościelnickalogger: Add -check-expected subcommand.
2021-08-12 github-actions... Bump version
2021-08-11 Marcelina Kościelnickatest/arch/{ecp5,ice40}/memories.ys: Use read_verilog...
2021-08-11 Marcelina Kościelnickamemory_dff: Recognize read ports with reset / initial...
2021-08-11 Marcelina Kościelnickaproc_memwr: Use the v2 memwr cell.
2021-08-11 Marcelina KościelnickaAdd v2 memory cells.
2021-08-11 github-actions... Bump version
2021-08-10 Marcelina Kościelnickakernel/mem: Introduce transparency masks.
2021-08-10 Michael SingerAllow optional comma after last entry in enum
2021-08-10 github-actions... Bump version
2021-08-09 Marcelina KościelnickaRefactor common parts of SAT-using optimizations into...
2021-08-08 github-actions... Bump version
2021-08-07 Marcelina Kościelnickaopt_merge: Use FfInitVals.
2021-08-07 github-actions... Bump version
2021-08-06 Marcelina Kościelnickaverilog: Support tri/triand/trior wire types.
2021-08-05 github-actions... Bump version
2021-08-04 Marcelina Kościelnickamemory_share: Don't skip ports with EN wired to input...
2021-08-04 github-actions... Bump version
2021-08-03 Marcelina Kościelnickamemory_bram: Move init data swizzling before other...
2021-08-03 github-actions... Bump version
2021-08-02 Miodrag MilanovicRequire latest verific
2021-08-02 github-actions... Bump version
2021-08-01 Marcelina Kościelnickabackend/verilog: Add alternate mode for transparent...
2021-08-01 Marcelina Kościelnickamemory_bram: Some refactoring
2021-07-31 github-actions... Bump version
2021-07-30 Miodrag MilanovićUpdate version.yml
2021-07-30 Maciej DudekFixes xc7 BRAM36s
2021-07-30 Zachary Snowproc_rmdead: use explicit pattern set when there are...
2021-07-30 Zachary Snowgenrtlil: add width detection for AST_PREFIX nodes
2021-07-30 github-actions... Bump version
2021-07-29 Marcelina Kościelnickaopt_lut: Allow more than one -dlogic per cell type.
2021-07-29 Zachary Snowverilog: save and restore overwritten macro arguments
2021-07-29 github-actions... Bump version
2021-07-28 Marcelina Kościelnickaverilog: Emit $meminit_v2 cell.
2021-07-28 Marcelina Kościelnickabackends/verilog: Support meminit with mask.
2021-07-28 Marcelina Kościelnickamemory: Introduce $meminit_v2 cell, with EN input.
2021-07-28 github-actions... Bump version
2021-07-27 Marcelina Kościelnickaproc: Run opt_expr at the end
2021-07-27 Marcelina Kościelnickaopt_expr: Propagate constants to port connections.
2021-07-27 github-actions... Bump version
2021-07-26 Miodrag MilanovicAdd version bump workflow
2021-07-21 Miodrag MilanovicUpdate to latest verific
2021-07-20 Rupert SwarbrickUse new read_id_num helper function elsewhere in hierar...
2021-07-20 Rupert SwarbrickExtract connection checking logic from expand_module...
2021-07-20 whitequarkMerge pull request #2885 from whitequark/cxxrtl-fix...
2021-07-20 whitequarkMerge pull request #2884 from whitequark/cxxrtl-fix...
2021-07-20 whitequarkcxxrtl: treat wires with multiple defs as not inlinable.
2021-07-20 whitequarkcxxrtl: treat assignable internal wires used only for...
2021-07-20 whitequarkMerge pull request #2881 from whitequark/cxxrtl-sideway...
2021-07-19 whitequarkcxxrtl: escape colon in variable names in VCD writer.
2021-07-18 whitequarkMerge pull request #2880 from whitequark/cxxrtl-fix...
2021-07-18 whitequarkcxxrtl: add debug_item::{get,set}.
2021-07-17 whitequarkMerge pull request #2879 from whitequark/cxxrtl-fix...
2021-07-17 whitequarkcxxrtl: treat internal wires used only for debug as...
2021-07-16 Rupert SwarbrickAdd support for parsing the SystemVerilog 'bind' construct
2021-07-16 whitequarkMerge pull request #2874 from whitequark/cxxrtl-fix...
2021-07-16 whitequarkMerge pull request #2873 from whitequark/cxxrtl-fix...
2021-07-16 whitequarkMerge pull request #2872 from whitequark/cxxrtl-fix...
2021-07-16 whitequarkcxxrtl: run hierarchy pass regardless of (*top*) attrib...
2021-07-16 whitequarkcxxrtl: emit debug items for unused public wires.
2021-07-16 whitequarkcxxrtl: don't expect user cell inputs to be wires.
2021-07-16 whitequarkMerge pull request #2871 from whitequark/cxxrtl-fix...
2021-07-16 whitequarkcxxrtl: don't mark buffered internal wires as UNUSED...
2021-07-16 whitequarkMerge pull request #2870 from whitequark/cxxrtl-fix...
2021-07-15 whitequarkcxxrtl: mark dead local wires as unused even with inlin...
2021-07-15 Zachary Snowsv: fix two struct access bugs
2021-07-15 Rupert SwarbrickAdd a test for interfaces on modules loaded on-demand
2021-07-15 Rupert SwarbrickExtract missing module support in hierarchy.cc to a...
2021-07-14 whitequarkMerge pull request #2866 from rswarbrick/found-init
2021-07-14 Rupert SwarbrickDelete unused found_init variable
2021-07-13 Marcelina Kościelnickakernel/mem: Add a coalesce_inits helper.
2021-07-12 GCHQDeveloper560Add support for the Bitwuzla solver
2021-07-12 Marcelina Kościelnickakernel/mem: Use delayed removal for inits as well.
2021-07-12 Marcelina Kościelnickakernel/mem: Add documentation for more helper functions.
2021-07-12 Marcelina Kościelnickacxxrtl: Support memory writes in processes.
2021-07-12 Marcelina Kościelnickacxxrtl: Add support for memory read port reset.
2021-07-12 Marcelina Kościelnickacxxrtl: Add support for mem read port initial data.
2021-07-12 Marcelina Kościelnickacxxrtl: Convert to Mem helpers.
2021-07-12 Marcelina Kościelnickakernel/mem: Commit new values of attributes in emit.
2021-07-12 Marcelina Kościelnickakernel/mem: Make the Mem helpers inherit from AttrObject.
2021-07-11 Marcelina Kościelnickartlil: Make Process handling more uniform with Cell...
2021-07-10 Marcelina Kościelnickaice40: Fix LUT input indices in opt_lut -dlogic (again).
2021-07-09 Miodrag MilanovicUpdate to latest Verific with extensions for initial...
2021-07-06 Zachary Snowsv: fix a few struct and enum memory leaks
2021-07-06 gatecatecp5: Add DCSC blackbox
2021-07-05 Claire XenMerge pull request #2835 from YosysHQ/verific_command
2021-07-05 XiretzaMakefile: allow running multiple sanitizers at once
2021-07-05 XiretzaMakefile: use git/make -C instead of cd
2021-07-05 XiretzaMakefile: pass PRETTY=0 to ABC
2021-07-05 XiretzaMakefile: don't bake DESTDIR into libyosys DT_SONAME
2021-07-05 XiretzaMakefile: clean up PYOSYS configuration
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