litex.git
2011-12-16 Sebastien Bourdeauducqverilog: user-definable reset and clock
2011-12-16 Sebastien Bourdeauducqfhdl: simpler syntax
2011-12-16 Sebastien BourdeauducqPay a bit more attention to PEP8
2011-12-13 Sebastien Bourdeauducqwishbone2csr: wait for WB deack
2011-12-13 Sebastien Bourdeauducqtimeline: only trigger in rest state
2011-12-13 Sebastien Bourdeauducqexamples: Wishbone interconnect test bench
2011-12-13 Sebastien Bourdeauducqverilog: use blocking assignment in combinatorial process
2011-12-13 Sebastien Bourdeauducqwishbone: decoder: fix slave cyc generation in register...
2011-12-12 Sebastien Bourdeauducqwishbone2csr: fix double-write bug
2011-12-12 Sebastien Bourdeauducqwishbone: only send ack to the active master in arbiter
2011-12-12 Sebastien Bourdeauducqfhdl: allow a namespace to be specified for Verilog...
2011-12-11 Sebastien Bourdeauducqfhdl: support Constant parameters for Verilog conversion
2011-12-11 Sebastien Bourdeauducqfhdl: fix list references (thanks Lars)
2011-12-11 Sebastien Bourdeauducqbus: fix CSR interconnect data readback
2011-12-11 Sebastien Bourdeauducqbus: 14-bit CSR addresses
2011-12-11 Sebastien Bourdeauducqbank: fix csrgen address decoder
2011-12-11 Sebastien Bourdeauducqbus: Wishbone to CSR bridge
2011-12-11 Sebastien Bourdeauducqcorelogic: timeline module
2011-12-11 Sebastien Bourdeauducqfhdl: remove broken fragment iadd
2011-12-11 Sebastien Bourdeauducqconvtools: insert reset on variables
2011-12-10 Sebastien Bourdeauducqautofragment: remove debug
2011-12-10 Sebastien Bourdeauducqfhdl: autofragment
2011-12-10 Sebastien Bourdeauducqfhdl: fix += for empty fragment
2011-12-10 Sebastien Bourdeauducqfhdl: pad support in fragments
2011-12-09 Sebastien Bourdeauducqwishbone: decoder + shared bus interconnect
2011-12-09 Sebastien Bourdeauducqfhdl: replication support
2011-12-08 Sebastien Bourdeauducqwishbone: arbiter
2011-12-08 Sebastien Bourdeauducqsimplebus: export GetSigName function
2011-12-08 Sebastien Bourdeauducqcorelogic: multimux module
2011-12-08 Sebastien Bourdeauducqverilog: handle default in case statements
2011-12-08 Sebastien Bourdeauducqfhdl: improve automatic signal naming
2011-12-08 Sebastien BourdeauducqCorelogic conversion example
2011-12-08 Sebastien Bourdeauducqcorelogic: MC divider module
2011-12-08 Sebastien Bourdeauducqfhdl: support negation operator
2011-12-08 Sebastien Bourdeauducqverilog: fix unary operator conversion
2011-12-08 Sebastien Bourdeauducqcorelogic: round-robin module
2011-12-08 Sebastien BourdeauducqNamed buses
2011-12-08 Sebastien Bourdeauducqwishbone: add missing SEL
2011-12-08 Sebastien Bourdeauducqinstances: signal override
2011-12-08 Sebastien BourdeauducqWishbone declarations
2011-12-08 Sebastien BourdeauducqSimple bus base class
2011-12-08 Sebastien BourdeauducqInstance support
2011-12-07 Sebastien Bourdeauducqfhdl: fix implicit slice index
2011-12-07 Sebastien Bourdeauducqfhdl: cleanup value bv
2011-12-05 Sebastien BourdeauducqVariable conversion
2011-12-05 Sebastien BourdeauducqCleanup
2011-12-05 Sebastien BourdeauducqCase support + register bank generator
2011-12-04 Sebastien BourdeauducqCSR bus definitions
2011-12-04 Sebastien BourdeauducqExamples folder
2011-12-04 Sebastien BourdeauducqReset insertion
2011-12-04 Sebastien BourdeauducqVerilog generator
2011-12-04 Sebastien BourdeauducqInitial import, FHDL basic structure, divider example